Micrel, Incorporated

Pakal Technologies, LLC

Other

Paul McKay Moore

Vladimir Rodov

Richard A Blanchard

David Raymond Zinn

Martin J Alter

Jayasimha Prasad

Woytek Tworzydlo

Gary Michael Hurtz

In a vertical power device with trenched insulated gates, there is an npnp layered structure. The vertical gates turn on the device with a suitable gate bias to conduct a current between a top electrode and a bottom electrode. In an example, implanted n+ source regions are formed in the top surface within a p-well. Between some gates, the overlying dielectric is opened up, by etching, to expose distributed p-type contact regions for the p-well. The dielectric is also opened up to expose areas of the n+ source regions. The top electrode metal directly contacts the exposed p-type contact regions and the n+ source regions to provide distributed emitter-to-base short across the cellular array to improve device performance in the presence of transients. The p-contact regions are isolated from the n+ source regions, prior to the deposition of the metal electrode, due to the p-type contact regions not abutting the n+ source regions.

Vertical insulated gate power switch with isolated base contact regions

Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity.

Insulated trench gates with multiple layers for improved performance of semiconductor devices

A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n− type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

Etch stop layer for injecting carriers into drift layer for a vertical power device

In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p&#x2212;type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Insulated trench gates with dopants implanted through gate oxide

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n&#x2212; buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n&#x2212; buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n&#x2212; buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

Anti-parallel diode formed using damaged crystal structure in a vertical power device

An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

NPNP layered MOS-gated trench device having lowered operating voltage

A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1&#xd7;, 2&#xd7;, and 4&#xd7;, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Insulated gate power device with independently controlled segments

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n&#x2212; drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.

Insulated gate turn-off device with designated breakdown areas between gate trenches

A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

DMOS transistor with trench schottky diode

The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.

LDMOS transistor with asymmetric spacer as gate

The present invention provides an FET which includes an epitaxial layer and first and second body regions formed over the epitaxial layer. Further, the FET includes a first trench formed in the epitaxial layer between the first and the second body regions. The FET also includes a conductive layer formed on the sidewall of the first trench. The conductive layer acts as gate of the FET. The FET also includes a second trench formed at the bottom of the first trench, a first dielectric layer formed over the conductive layer and on the sidewall of the second trench, and a second dielectric layer formed on the first dielectric layer. Further, the FET includes a conductive layer, which acts as drain, deposited in the first and the second trenches. The FET also includes first and a second source regions formed in the first and second body regions, respectively.

Split slot FET with embedded drain

A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor.

Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region

A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the first dopant region, growing a first isolation region over a first portion of the substrate, the first dopant region, and the second dopant region, growing a second isolation region over a second portion of the substrate, the first dopant region, and the second dopant region, defining a contact region in the second dopant region, the contact region extending between the first isolation region and the second isolation region, depositing a gate oxide layer to form a first gate dielectric atop the first isolation region and a portion of the contact region, and overlaying a gate conductive layer on top of the gate oxide layer to form a first gate conductor atop the first gate dielectric.

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Fremont, CA, United States of America

Paul McKay Moore