Altera Corporation

Paul McHardy

Scott James Brissenden

Deshanand Pratap Singh

Valavan Manohararajah

Terry Borer

Gabriel Quan

Ivan Hamer

Stephen D Brown

Kevin Chan

Ian Chesal

Chris Sanford

Karl Schabas

A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.

Method and apparatus for automatic hierarchical design partitioning

A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.

Method and apparatus for performing layout-driven optimizations on field programmable gate arrays

A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.

Method and apparatus for performing logic replication in field programmable gate arrays

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Toronto, Canada

Paul McHardy