Motorola Corporation

Freescale Semiconductor,inc.

Paul M Winebarger

Lianjun Liu

Lisa H Karlin

Alex P Pamatat

Mark A Zaleski

Charles W Stager

Robert F Steimle

Thomas Sachio Kobayashi

Gregory S Ferguson

Jeffrey J Sultemeier

Troy B Morrison

Joseph E Page

Christopher A Turman

A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (B,D) formed in different layers of a multi-layer semiconductor structure () and one or more cap devices () bonded to the multi-layer semiconductor structure () to protect any exposed inertial transducer element from ambient environmental conditions.

MEMS fabrication process with two cavities operating at different pressures

A wafer structure () includes a device wafer () and a cap wafer (). Semiconductor dies () on the device wafer () each include a microelectronic device () and terminal elements (). Barriers () are positioned in inactive regions () of the device wafer (). The cap wafer () is coupled to the device wafer () and covers the semiconductor dies (). Portions () of the cap wafer () are removed to expose the terminal elements (). The barriers () may be taller than the elements () and function to prevent the portions () from contacting the terminal elements () when the portions () are removed. The wafer structure () is singulated to form multiple semiconductor devices (), each device () including the microelectronic device () covered by a section of the cap wafer () and terminal elements () exposed from the cap wafer ().

Cavity based packaging for MEMS devices

Method of fabricating a semiconductor device that limits damage to elements of the semiconductor device that are exposed during processing

A chemical-mechanical-polishing (CMP) process in which a metal interconnect material (47) is polished to form a metal plug (48) includes the application of titanium to the surface of a polishing pad (14) of a polishing apparatus (10). Titanium metal is applied to the surface of the polishing pad (14) by either abrasively applying titanium by use of a titanium block (32) attached to a rotating disk (26), or by a titanium body (23, 25) integrated with a carrier ring (23). Alternatively, titanium can be applied by impregnating a felt layer (52) with titanium particles (56), or by adding titanium directly to the polishing slurry (50).

Metallized pad polishing process

A selective cleaning process for fabricating a semiconductor device includes the steps of processing a semiconductor substrate (10) and introducing metal contaminants (22) by contacting the semiconductor substrate (10) with a polishing slurry during a polished planarization process. The metal contaminants (22) are removed by applying a cleaning solution including an organic solvent and a compound containing fluorine. The chemical constituents of the cleaning solution are substantially unreactive with metal interconnect material (12) underlying dielectric layers (18) present on the semiconductor substrate (10). The preferred cleaning solution comprises an aqueous solution of ethylene glycol and ammonium fluoride.

Selective cleaning process for fabricating a semiconductor device

A semiconductor substrate (48) and a block of optical quartz (50) are simultaneously polished. An interferometer (22), in conjunction with a data processing system (16), are then used to monitor the thickness and the polishing rate of the optical quartz block. This allows the endpoint of the polishing process to be automatically and reproducibly detected, and it also allows the polishing rate of the semiconductor substrate (48) to be automatically adjusted during the polishing process.

Method for polishing a substrate

A method for planarizing a layer (18) begins by forming a layer (18) over a wafer having a substrate (12). Layer (18) has a surface topography which is not planar. A layer of material (20) is formed over the layer (18). The layer of material (20) has a surface which is more planar than the surface of layer (18). The surface of material (20) is transferred into the layer (18) by etching the layer (18) and the material (20) at approximately the same etch rate. The same etch rate is achieved by monitoring one of either the surface of the wafer or the etch environment of an etch system chamber. A computer-controlled feedback path alters an etch chemistry or etch environment to maintain the etch rates within an etch rate tolerance which is also referred to as a process window. By monitoring and altering the etch environment and/or the etch chemistry to maintain a process window, an optimal planar surface is achieved for layer (18).

Method for processing a layer of material while using insitu monitoring

A process for fabricating a semiconductor device uses re-ionized water, such as carbonated water, to rinse the device while preventing microcorrosion of metal layers. In one embodiment of the invention, a semiconductor wafer is provided having an overlying metal layer and a patterned layer overlying the overlying metal layer. Selected portions of the overlying metal layer are etched using the patterned layer as an etch mask. The patterned layer is removed by immersing the device in an organic solution without affecting the remaining metal layer. The device is then rinsed in a reservoir of re-ionized water to remove the organic solution from the device while preventing microcorrosion of the remaining metal layer.

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Austin, TX, United States of America

Paul M Winebarger