Texas Instruments Corporation

Paul M Urbanus

Jeffrey Brian Sampsell

Robert J Gove

Donald B Doherty

Vishal Markandey

Stephen Wesley Marshall

Henry D Hendrix

William E Nelson

Venkat V Easwar

Gregory James Hewlett

Robert M Boysel

Scott D Heimbuch

Stephen G Kalthoff

Masaho Asahara

A method and system for adjusting the brightness and contrast of a digital pulse-width modulated display without scaling the input image data. Brightness is adjusted by changing the duty cycle of a displayed pixel either by altering the bit display durations, or by turning the pixel on during blanking periods The contrast ratio may be altered by changing the display duration of at least one of the MSBs differently than the display duration of at least one of the LSBs. Contrast may be increased by extending the MSB display periods and shortening the LSB display periods Contrast may be decreased by shortening the MSB display periods and extending the LSB display periods The color tint of the displayed image may be altered by individually changing the brightness of the constituent colors.

Brightness and contrast control for a digital pulse-width modulated display system

An SLM-based video receiver (,) receives a video input of some standardized format at a signal interface unit (,) and passes the input to a processor (,). The processor (,) performs analog-to-digital conversion if the pixel data is analog and also performs other enhancements to prepare the pixel data for loading into a video memory (,). The pixel data from the processor (,), representing a field of pixel data, is stored into the memory (,) for loading into rows of pixel elements of a spatial light modulator (,). The spatial light modulator (,) receives the pixel data in rows and each individual pixel element responds accordingly. The pixel elements of the spatial light modulator (,) emit light or reflect light from a source (,) and generate a video frame for display on a screen (,). By exploiting the addressing functions of the spatial light modulator (,), the SLM-based video receiver (,) displays a video frame using a field of pixel data.

Displaying video data on a spatial light modulator

A display memory (,) for a display system (,) having a spatial light modulator (SLM) (,). The memory (,) receives data in pixel format and delivers the data to the SLM (,) in bit-plane format. The memory (,) avoids the need for double buffering by reading out bit-planes that are comprised partly of data from one data from and partly of data from an adjacent data frame.

Single-frame display memory for spatial light modulator

A method for printing or exposing photosensitive media is disclosed herein. The method uses standard spatial light modulators with standard addressing circuitry. The data is written to the device for the first row, the photosensitive media is exposed to the light reflected from the device, and the device is turned off. The data from the first row is then written to the second line of the device, and new data is loaded into the first line of the device. The media is again exposed. This is repeated until the entire region of the drum is completely exposed. The device can be repositioned to cover a different region of the drum and the process would be repeated.

Non-systolic time delay and integration printing

It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual part of the system and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

DMD architecture and timing for use in a pulse-width modulated display

An SLM-based digital display system (10) having a graphics display subsystem (13 and 18) for closed captioning, on-screen displays, and other graphics images that are overlaid on the video image. The graphics display subsystem (13 and 18) has a graphics processor (21) that prepares the graphics data, which is inserted into the video data path after video data processing and prior to a look-up table unit (27). A select logic unit (24) provides a control signal to a multiplexer (26) that selects between video data and graphics data for input to the look-up table unit (27). The look-up table unit (27) performs its mapping according to the type of data received, such as by linearizing video data or palletizing graphics data.

Graphics subsystem for digital television

A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

Multiplexed memory timing with block reset and secondary memory

A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j). One of each channel signal processors (22a ) through (22d) may be coupled to two of first in-first out buffer memories (34a) through (34j). Additionally, each formatter (24a) through (24c) may comprise channel data format units (38a) through (38d), each associated with a channel of, for example, display (24a). Channel data format units (38a) through (38d) are coupled to appropriate of first in-first out buffer memories (34a) through (34j) via multiplexers (36a) through (36d). Each formatter (24a) through (24c) may remove overlap between channels of system (10) and may format the processed video signal into appropriate channels for displays (26a) through (26c).

Video data formatter for a multi-channel digital television system

An SLM-based video receiver (10) receives a video input on a field-by-field basis at a signal interface unit (11) and passes the input to a processor (12). The processor (12) performs analog-to-digital conversion if the pixel data is analog and also performs other enhancements to prepare the pixel data for loading into a video memory (14). Pixel data from the processor (12), representing a field of pixel data, is stored into the memory (14) for loading into rows of pixel elements of a spatial light modulator (16). The spatial light modulator (16) receives the pixel data in rows. The addressing functions of the spatial light modulator (16) are used to generate additional display rows of pixel data per field. Thus, the SLM-based video receiver (10) displays a video frame having more lines than the field of pixel data.

Displaying video data on a spatial light modulator with line doubling

A frame buffer for a spatial light modulator in a image display system. The frame buffer is comprised of video random access memory devices (VRAM's) having sections of VRAM rows that receive a value from one bit position of all display rows. An allocation circuit provides addresses for filling said VRAM rows when data is being written to the frame buffer, updates an address memory as VRAM rows are emptied, and provides addresses for mapping VRAM rows to display rows of the spatial light modulator when data is being read out of the frame buffer.

Dynamic memory allocation for frame buffer for spatial light modulator

A method and circuit for improving a video signal. They can be used to nullify the gamma correction applied at the broadcast end for cathode-ray tube signals when using a spatial light modulator display. Additionally, the method and circuit can be used to generally improve the quality of the display for computer monitors or other formats that do not require the gamma nullification.

Method and apparatus to improve a video signal

It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual parts of the system, and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

DMD architecture and timing for use in a pulse width modulated display

A method and structure for providing system control to a spatial light modulator display are disclosed. The control functions are divided into smaller, easier to implement control blocks and coordination between them is provided. The smaller blocks are a memory controller, a modulator controller and a formatter controller.

Growing community of inventors

Dallas, TX, United States of America

Paul M Urbanus