Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

Paul M Goodwin

Donald W Smelser

David A Tatosian

Kurt M Thaller

Barry A Maskas

Michael A Gagliardo

Stephen R Van Doren

Nitin Dhiroobhai Godiwala

James E Tessari

John J Lynch

Jeffrey A Metzger

Kumar Chinnaswamy

Stephen R VanDoren

John A Nerl

Stephen Van Doren

Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping &ldquo;fill&rdquo; requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the &ldquo;victim&rdquo; data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.

Cache memory exchange optimized memory organization for a computer system

A memory system has a plurality of interleaved memory ranks that use SDRAMs requiring a periodic refresh, and an arbiter which controls access to the memory ranks and restricts access to a memory rank being refreshed. The memory ranks are interleaved on a memory module. Counting refresh registers on each memory module are associated with the module's memory ranks. The arbiter has its own counting refresh register. At regular intervals, the arbiter broadcasts a refresh signal along with a refresh address to the modules via a transaction bus. The refresh address provided by the arbiter is latched by the refresh registers which then begin counting at a pre-programmed interval. A refresh to a particular memory rank is triggered when a refresh register associated with the memory rank matches a unique identifier assigned to that rank. The arbiter uses its refresh register to identify the memory rank being refreshed, allowing the arbiter to restrict access to that memory rank. As a result, the memory ranks are refreshed sequentially without ongoing control by the arbiter.

Memory refresh control system

Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping 'fill' requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the 'victim' data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.

An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

Method and apparatus for delaying victim writes in a switch-based

A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Bus interface slicing mechanism allowing for a control/data path slice

A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous dynamic random access memory devices. The technique involves obtaining, independently of a central controller, time phase identifiers that respectively correspond to the memory modules, and reducing the normal operating clock rate to a reduced clock rate. The technique further involves executing, in the memory modules, self test transactions in different time phases depending on the obtained time phase identifiers. The memory modules initiate execution of self test transactions at the reduced clock rate. Multiple memory modules execute self test transactions in each of the different time phases. Each memory module executes self test transactions that alternately access the multiple arrays of that memory module. Preferably, the time phase identifiers are based on module identifiers that uniquely identify the memory modules.

Method and apparatus for a low power self test of a memory subsystem

Printed Circuit Board fabrication costs are decreased, and device placement densities are increased by the use of well structures designed for receiving components such as capacitors on portions of the PCB directly beneath integrated circuit packages having very low vertical profiles. With such an arrangement it is possible to use newer low profile packages and still place a capacitor under the integrated circuit package for reduced area consumption and improved inductance and circuit cycle times. Further advantages of the present arrangement include a reduction in the number of vias that need to be drilled in the PCB to make capacitor attachments, a consequent improvement in PCB inductance and parasitic capacitance, and improved electrical properties for voltage reference planes and routing layers.

Printed circuit board having a well structure accommodating one or more

An adjustable filter for a computing system having memory error detecting and correcting features selectively masks user-specified errors, thereby preventing storage of such errors in a control and status register (CSR). The invention includes a command and data register 102; a CSR 103; an error detecting and correcting circuit 108, including a check bit generator 108a, an error detecting circuit 108b, and an error correcting circuit 108c; a memory module 114; and filter logic 300. The contents of a filter control register 220 of the CSR 103 operate to specify a particular error which is to be 'filtered'. The filter logic 300 includes a plurality of logic gates that compare the user-specified signals stored in the register 220 with error-related signals reported by the error detecting circuit 108b. If the signals match, information associated with the detected error is prevented from being stored in the CSR 103.

Adjustable filter for error detecting and correcting system

Bus interface slicing mechanism allowing for a control/data-path slice

A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. One feature is appending page mode read cycles to a normal read, in order to fill the FIFO. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the data in the stream buffer is protected by EDC.

Memory stream buffer with variable-size prefetch depending on memory

A read buffering system employs FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When the system sees a read command from the CPU, it stores an incremented value of the address of the read command in a history buffer and marks the entry as valid. The system detects a stream when a subsequent read command specifies an address that matches the address value stored in the history buffer. Upon detecting a stream, the system fetches data from DRAMs at addresses that follow the address of the subsequent read command, and stores it in a FIFO. However, to reduce unnecessary prefetching, the system looks for a read X, write X, read X+1 (where X and X+1 designate addresses) succession of commands so as to prevent them from creating a stream. This succession occurs often and qualifies as a stream, but is seldom followed by other reads that maintain the stream. The system checks for this succession by comparing an incremented value of the address of the write command with each valid address value stored in the history buffer. A match causes the system to invalidate the history buffer entry containing the matched address value. This effectively disables the use of this address value for detecting a stream upon subsequent read commands and, consequently, for prefetching data from memory.

Method for increased performance from a memory stream buffer by

A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis. However, the addresses of those reads that hit in the stream buffer are not entered, thus improving the overall efficiency of the stream buffer. Also, the memory refresh controller treats stream buffer hits as memory refresh opportunities. Finally, a block of control/status registers within the memory controller is accessible in two distinct address ranges, so that the memory controller may easily be used in different hardware configurations.

Memory stream buffer

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. One feature is appending page mode read cycles to a normal read, in order to fill the FIFO. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the data in the stream buffer is protected by EDC.

System for sequential read of memory stream buffer detecting page mode

The operation of a stream buffer varies depending on whether a normal operation mode or a test mode is selected. In the normal operation mode, the stream buffer is read from only when the data requested by a CPU read has been determined to reside there, and the stream buffer location read from is the location determined to contain the requested data. This determination is made by comparing the address of the read request with addresses of the data stored in the stream buffer. Also, the stream buffer is written with memory data in response to a read that misses the stream buffer, and the location written to is one that has been allocated to receive the incoming memory data. Two different buffer allocation methods are shown, first-in-first-out (FIFO) and least-recently-used (LRU). During the test operation mode, the stream buffer is written to and read from directly by the CPU at locations specified in the write and read requests, without regard to the data presence determination and the allocation that take place in the normal operation mode. The method provides a straightforward way of testing the stream buffer during system operation by bypassing some normal functions during test mode in favor of direct stream buffer access by the CPU.

Method of using stream buffer to perform operation under normal

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the stream buffer is protected by EDC.

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Littleton, MA, United States of America

Paul M Goodwin