General Electric Company

General Electric Corporation Gmbh

Paul M Espelage

Loren H Walker

David L Lippitt

Bimal K Bose

James M Nowak

James Patrick Lyons

Vlatko Vlatkovic

Leland C Tupper

John D D'Atre

Albert Andreas Esser

John S Sicko

Franz C Zach

Robert William Delmerico

John H Cutler

Jing Wang

Herbert W Weiss

B Paul Chausse

Yifan Zhao

William G Wright, Deceased

Fei Fred Wang, Sr

A high power motor drive converter includes: a five level hybrid NPC output power conversion stage including three NPC phase bridges having switches and coupled in a wye configuration through a converter neutral point, each NPC phase bridge receiving power on a respective direct current bus; three isolated split series-connected DC capacitor banks each coupled in parallel to a respective one of the three NPC phase bridges; and a controller for selecting switch positions with active control of neutral voltages. The controller is adapted to select switch positions using feedforward sine-triangle modulation with third harmonic injection, zero sequence injection, and/or discontinuous modulation injection.

Five level high power motor drive converter and control system

A three-level NPC converter includes at least one phase leg including four series coupled electrical switches having a first pair junction between the first two switches and a second pair junction between the second two switches. First and second inner switch snubber capacitors are coupled in series at a neutral junction. First and second inner switch snubber diodes are respectively coupled to the first and second pair junctions and respectively coupled at first and second inner diode-capacitor junctions to the first and second inner switch snubber capacitors. First and second inner switch snubber resistors are respectively coupled between the first and second inner diode-capacitor junctions and respective portions of a DC bus. In one embodiment, the NPC converter further includes first and second outer switch snubber diodes coupled between respective first and second inner diode-capacitor junctions and respective portions of the DC bus. This embodiment may further include first and second outer switch snubber capacitors coupled in parallel with respective first and second inner switch snubber capacitors.

Voltage clamp snubbers for three level converter

A high power motor drive converter includes a three level neutral point clamped (NPC) output power conversion stage including switches; a split series connected DC capacitor bank coupled in parallel with the NPC output power conversion stage; and a controller for selecting switch positions for controlling the NPC output power conversion stage and controlling a neutral voltage balance of the DC capacitor bank by using space vector modulation and predictive charge calculations.

High power motor drive converter system and modulation control

An induction motor drive having source and load side converters with individual control channels for the respective converters includes a cross tie arrangement between the channels for increased system stability.

Cross tie for induction motor drive

An induction motor drive including a current source inverter system having controlled turn on and turn off semiconductors in a load side inverter selectively places notches in the waveshape of the current supplied to the parallel combination of the motor and a capacitor bank for the minimization of harmonics.

Method and apparatus for induction motor drive

A power conditioner having a source and load converter each using a phase-locked loop to control their respective converter firings achieves synchronization with a supply mains by determining the phase error between supply mains and motor voltages by obtaining the instantaneous difference between the output signals of the source and load phase locked loops. This phase error is passed through a simple gain and summed with a speed regulator setpoint, which now becomes an inverter frequency regulator with the nominal setpoint being the supply mains frequency. The voltage amplitude error between the supply mains and the motor is obtained by comparing the absolute value of the source voltage with the properly scaled absolute value of the integrated motor voltage and this error signal is input to the flux regulator in a synchronous or induction motor controller in place of the normal input when not synchronizing.

Control for bumpless transfer of an AC motor between a solid-state

A single microcomputer controls the firing time determination for two independent current regulators for two six pulse AC/DC converters which are part of a twelve pulse parallel controlled current inverter (CCI) AC motor drive. A very short high priority interrupt occurs when a motor channel source converter thyristor fires. This interrupt calls a longer, low priority current regulator interrupt informing it that a master channel source converter thyristor has just been fired. The current regulator causes a count to be loaded into a master fire counter and also loads a firing mask into a hardware latch or buffer. When the master fire counter times out the next thyristor pair of the master channel source converter is fired directly out of hardware. Similarly, there is a separate slave channel fire counter loaded after the current regulator is called by a short high priority interrupt when a thyristor in the slave channel source converter fires.

Twelve pulse AC motor drive

A controlled current inverter (CCI) induction motor drive is controlled by controlling motor current and the angle between motor flux and motor current. The angle between motor flux and current is derived directly via a microcomputer phase-locked loop synchronized to the integrated motor voltage. The delay between the application of a firing signal to a thyristor and the initiation of line current is determined and compensated for to achieve the desired angle between motor flux and motor current.

Phase-locked loop control of an induction motor drive

A method of starting an AC motor from any initial speed using open loop control is provided. Sufficient current is provided to the motor so that motor flux can be developed. The frequency provided to the AC motor is varied and the stator frequency at which the motor peak flux occurs is determined. A transition to a control responsive to an external command at approximately the stator frequency at which the peak flux occurred is made.

Start-up control for an induction motor drive

A microprocessor based pulse-width modulated variable speed drive control system providing optimal switching angles based on minimizing r.m.s. current ripple. In addition, a closed loop double deadband control interacts with the optimal switching angles to insure close following of a desired function of a specified variable to be controlled.

Method for providing adaptive control of variable speed AC motor drives

A fault protective system for a load commutated inverter motor drive including an AC to DC source side converter coupled from an AC source to a DC to AC load side converter via a DC link circuit and wherein the load side converter supplies AC power of varying magnitude and frequency to the synchronous motor load. A pair of microcomputers interlinked by a common digital memory respectively control the inverters and interface with hardware type sensor means for detecting the occurrence of a plurality of different types of faults. Additionally, a number of stored instructional sets or programs are respectively included in both microcomputers to detect by software means another plurality of faults. The detection of a fault on either side of the link circuit is communicated to the respective computer which subsequently communicates with the other microcomputer to effect a coordinated protective action in response to thyristor cell failures, circuit failures, and abnormal operating conditions. Cell failure faluts include those instances where a thyristor cell actually fails due to an open or short circuit as well as those cases where a cell fails to commutate properly due to firing strategy problems. Cirucit failures include open and short circuits both in the supply line and the motor leads, while abnormal operating conditions involve such things as low line voltage or excessive motor voltage.

Coordinated load commutated inverter protection system

A load commutated inverter synchronous motor drive system wherein a thyristor firing control of the inverter is determined by the amplitude of pesudo flux waveforms which are derived from the integral of the line voltages coupling the inverter to the motor being driven. A firing strategy is provided based on the premise that optimum thyristor firing in a load commutated inverter operating at a leading power factor occurs at a point just below the peak of the forthcoming pseudo flux waveform which point comprises an amount of volt-seconds necessary to effect current commutation plus a nominal safety margin. The determination and control is implemented, preferably, in a software phase lock loop but can, when desirable, be implemented in hardware.

Flux feedback firing control for a load commutated inverter

The load side converter or inverter in a load commutated inverter motor drive, including a source side AC to DC converter coupled to a DC to AC converter via a DC link circuit, is adapted to have at least three and preferably four modes of operation for bringing an AC motor load, and more particularly a synchronous motor, up to speed. In the preferred embodiment, the first mode constitutes an idle mode wherein the converter thyristors are maintained in a non-conducting state until commanded for normal operation. The second mode constitutes an initial start-up mode which assumes no knowledge of initial rotor position of the motor and simply utilizes a fixed low frequency firing signal to sequentially gate the thyristors using forced commutation to commutate the off-going thyristor. Thirdly, a second type of forced commutation mode is next entered into where the inverter frequency is synchronized to the rotor of the motor by sensing pseudo-flux waveforms until 5% to 10% of rated motor speed is achieved whereupon a fourth mode is entered into which comprises a self-commutation mode utilizing a phase lock loop operation using pseudo-flux wave zero crossings as synchronizing signals. In the three mode embodiment, the third mode is eliminated and the second mode modified to vary the load side converter frequency on a time basis until reaching some preset value (e.g., five (5) to fifteen (15) percent of motor rated frequency) at which time transition is made to the self-commutation mode.

Transitioning between multiple modes of inverter control in a load

A control system for powering an AC load such as a polyphase synchronous motor having at least two sets of three phase (3.phi.) windings. Each three phase winding set is powered by an independently operable six pulse load commutated inverter drive including a source side converter and a load side converter coupled together by means of a DC link and wherein the source side converter and the load side converter are operated in accordance with respective current and load angle regulators which respond to torque command signals generated by speed regulators. The two motor drives operate concurrently in separate control channels which are substantially independent of one another with the exception that in one embodiment, which is the preferred embodiment, the speed regulator and the motor terminal overvoltage regulator are cross-coupled to effect a balanced torque command and motor terminal voltage from each channel while still providing for continued motor operation by one of the motor drive channels in the event that the other becomes inoperative for any reason. In a second embodiment, one of two redundant speed regulators is adapted to provide a common torque command to both channels with the other speed regulator taking over in the event of the failure of said one speed regulator.

Twelve pulse load commutated inverter drive system

The effect of commutation notches 35 appearing in the nominally sinusoidal alternating current (AC) line-to-line voltage, for example, v.sub.ab used to synchronize the firing of thyristors in three phase, phase-locked power converters 12 and 14 is essentially eliminated by reconstructing the corrupted line-to-line voltage by summing the integral of the corrupted line-to-line voltage .PSI..sub.ab with a signal proportional to the product of the delta load current, for example, i.sub.ab and the commutation inductance L.sub.c. The composite waveform .PSI..sub.ab +i.sub.ab .times.L.sub.c) resulting from the summation has well defined zero crossings 41 from which synchronizing pulses are generated for synchronizing the phase-locked thyristor firing circuit 18 implemented by either software or hardware techniques. Additionally, the reconstructed waveform is used to control commutation, particularly in the control of a load side converter i.e. inverter 14 which is utilized in an AC motor drive system.

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Salem, VA, United States of America

Paul M Espelage