Intel Corporation

Paul M Brown

William H Clifford

James E Akiyama

Brent S Baxter

According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.

Memory micro-tiling request reordering

In some embodiments, a method includes generating blurred copies of an object by applying multi-texturing to the object during one pass through a graphics processing pipeline. In some embodiments, a graphics pipeline includes a texture memory and a graphics processor coupled to the texture memory. The texture memory provides a location to store texture information. The graphics processor provides processor to process the texture information by shifting and blending the texture information in one pass through the graphics processor to obtain shifted and blended texture information.

Growing community of inventors

University Place, WA, United States of America

Paul M Brown