Vixs Systems, Inc.

Motorola Corporation

Cirrus Logic Inc.

Vixs, Inc.

Paul M Astrachan

James Ward Girardeau, Jr

Mathew A Rybicki

John L Melanson

Lingli Zhang

Michael R May

Bradley Arthur Wallace

Donald C Anderson

Kyehyung Lee

Chia-Shiann Weng

Peter C Curtis

Walter U Kuenast

James Kelton

Tejasvi Das

Rahul Singh

Emmanuel A Marchais

Zhaohui He

Michael David Cave

Kiyoshi Kase

Bojan Subasic

David Yatim

Jose G Corleto

Qiang Li

James Robert Kelton

James Doyle

Joseph Y Chan

SuiWu Dong

Michael Chen

Kenneth C Weng

James C Lynch

Shawn Saleem

Anselmo Pilla

Chris A Aardema

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

Finite impulse response input digital-to-analog converter

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Digital pulse-width modulation (PWM) modulator with dynamically switchable code set for reduced total harmonic distortion and noise (THDN)

A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.

Apparatus and method of suppressing transient noise during transition for class-D amplifier system having one or more pulse width modulator output paths

A video scaling technique includes scaling a first dimension and a second dimension of a frame of video data to generate a scaled frame of video data. The scaling includes scaling the second dimension of a first portion of a frame of video data at a first rate to generate first scaled pixels and scaling the second dimension of a second portion of the frame of video data at the first rate to generate second scaled pixels. The scaling includes combining first output pixels based on the first scaled pixels and second output pixels based on the second scaled pixels to provide pixels of the scaled frame of video data at a second rate. The first rate is a fraction of the second rate.

Video scaling using multiple video paths

A receiver technique includes generating a DC offset compensation signal based on a frequency offset-compensated received signal and a frequency offset indication signal. The technique includes generating a DC offset-compensated received signal based on the DC offset compensation signal and a received signal. The frequency offset-compensated received signal may be generated using a first Coordinate Rotation DIgital Computer (CORDIC) responsive to the DC offset-compensated received symbol and the frequency offset indication signal. The DC offset compensation signal may be generated using a second CORDIC responsive to the frequency offset indication signal and a real-valued signal.

DC removal from multicarrier signals

A video processor includes a video stream translation module configured to generate a translated luminance value for a pixel of a current frame of a video data stream. The translated luminance value is based on a first luminance value for the pixel and a first translation matrix for the current frame of the video data stream. The video processor includes a filter configured to generate an output luminance value for the pixel based on the translated luminance value and a target translated luminance value for the pixel. The output luminance value may be based on a weighted average of the translated luminance value and the target translated luminance value using a first weighting factor. The video processor may include a first weighting factor generator configured to generate the first weighting factor based on luminance values of the current frame of the video stream.

Enhanced histogram equalization

A first video picture is translated based upon a first translation matrix to adjust a contrast of the first video image. A second translation matrix is determined based upon a first histogram of a second video picture. A third translation matrix is determined based upon the first translation matrix and the second translation matrix, and the video picture is translated based upon the third translation matrix. The translation matrix can be determined using a histogram that has been adjusted using a clipped histogram equalization technique.

Contrast control device and method therefor

A radio receiver includes a first diversity antenna structure, a second diversity antenna structure, a first RF receiver section, a second RF receiver section, a combining module, and a baseband processing module. The first diversity antenna structure provides the received inbound RF signals from one of the plurality of first antennas based on a first antenna selection signal to produce first received inbound RF signals. The second diversity antenna structure provides the received inbound RF signals from one of the plurality of second antennas based on a second antenna selection signal to produce second received inbound RF signals. The first and second RF receiver sections are operably coupled to convert the first and second received inbound RF signals into first and second inbound baseband signals, respectively. The combining module combines the first and second inbound baseband signals to produce inbound baseband signals.

Radio receiver having a diversity antenna structure

An encoded signal is modulated to produce a first radio frequency (RF) signal that is transmitted to a client module over a first transceiver channel when a first transceiver module is in a transceive mode. A channel scan is performed when the first transceiver module is in a scan mode. The encoded signal is modulated to produce a second RF signal and that is transmitted over a second transceiver channel when a second transceiver module is in a transceive mode.

Client module, multimedia server and methods for use therewith

A method and apparatus for synchronized channel transmission are disclosed. One embodiment of the method comprises: generating a first data stream and a second data stream; packetizing the first data stream to produce a first plurality of data packets; packetizing the second data stream to produce a second plurality of data packets; baseband processing the first plurality of data packets to produce a first plurality of symbols for each of the first plurality of data packets; baseband processing the second plurality of data packets to produce a second plurality of symbols for each of the second plurality of data packets; converting the first plurality of symbols into a first radio frequency signal; converting the second plurality of symbols into a second radio frequency signal; and synchronizing at least one of: generating the first and the second data streams, packetizing the first and second data streams, baseband processing the first and second plurality of data packets, and converting the first and second plurality of symbols.

Method and apparatus for synchronized channel transmission

A method and apparatus for adjusting symbol timing and/or symbol interval range of a receive burst of data within a radio receiver include processing that begins by receiving a radio frequency signal that includes bursts of data. The process then continues by determining a frequency offset for the burst of data based on a difference between the transmitter processing rate and a receiver processing rate. The processing then continues by determining a symbol timing offset and/or a symbol interval range offset based on the frequency offset. The process then proceeds by adjusting the initial symbol positioning and/or the symbol interval range offset of a burst of data based on the symbol timing offset.

Method and apparatus for adjusting symbol timing and/or symbol positioning of a receive burst of data within a radio receiver

A method for field error checking begins by decoding a predetermined pattern of a field of a frame to produce a decoded pattern. The method continues by determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding. The method continues by comparing the path metric distance with an excepted path metric distance for the predetermined state. The method continues by indicating a field error when the path metric distance compares unfavorably with the excepted path metric distance.

Error checking using a field of a frame

A method for detecting validity of a received signal begins by performing an auto-correlation on the received signal to produce an auto-correlation resultant. The process continues by performing a cross-correlation on the receive signal with a reference signal to produce a cross-correlation resultant. The process then continues by mathematically relating the auto-correlation resultant with the cross-correlation resultant to produce a mathematical correlation relationship. The process then proceeds by interpreting the mathematical correlation relationship to indicate whether the receive signal is valid or not.

Method and apparatus for accurately detecting validity of a received signal

A first direct current (DC) component of a first amplified representation of a received signal at an output of an amplifier set to a first gain setting is determined during a first expected idle period of a received signal. A second DC component of a second amplified representation of the received signal at the output of the amplifier set to the first gain setting is determined during a second expected idle period of the received signal. A first average DC component is determined based at least in part on the first and second DC components and a DC offset used by the amplifier when set to the first gain setting is adjusted based on a comparison of the first average DC component to one or more threshold values.

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Austin, TX, United States of America

Paul M Astrachan