Altera Corporation

Google Inc.

Paul Leventis

David Lewis

Vaughn Betz

Andy Louie Lee

Christopher F Lane

Cameron R McClintock

Brian D Johnson

Srinivas T Reddy

Richard G Cliff

Chris Lane

Chris Wysocki

Michael Chan

Alexander Marquardt

Bruce B Pedersen

Vikram Santurkar

Dov Shimon Zimring

Henry Kim

Ketan H Zaveri

Hyun Mo Yi

Clinton Smullen

Paul Lalonde

Joshua David Fender

Giles V Powell

Jeffrey T Watt

David Edward Jefferson

Philip Pan

Robert McCool

Aki Kuusela

David Cashman

Navid Azizi

Triet M Nguyen

Matthew L Rodgers

Thomas Yau-Tsun Wong

Benjamin Frenkel

Yaron Kretchmer

Jani Huoponen

Timothy Vanderhoek

Gordon Raymond Chiu

William Bradley Vest

Benjamin Gamsa

Jean-François Roy

Yin Chong Hew

Kamal Patel

Garret Kelly

Gregory Canessa

Jack Buser

Vaughn Timothy Betz

Cameron Mcclintock

Brian Johnson

Some implementations of this application are directed to a server system including one or more CPUs, a plurality of GPUs, main dynamic memory storing programs and data for use by the CPUs and/or GPUs during program execution, a static memory pool stored in a non-volatile memory, and a memory controller configured to manage the static memory pool. Each of the GPUs includes a local cache and is configured to access the static memory pool via the memory controller. The server system executes a plurality of gaming sessions for a gaming title in parallel on the one or more CPUs. Each of the plurality of gaming sessions is associated with a static data item stored in the static memory pool, and requires a graphics operation executable by a respective GPU using the static data item.

Memory management in gaming rendering

This application is directed to a method of managing processing capability of a server system having one or more processing cores that further include multiple processing slices. Upon receiving requests to initiate online gaming sessions, the server system allocates each processing slice of the processing cores to a subset of the online gaming sessions to be executed thereon. A first processing slice is allocated to a first subset of the online gaming sessions including a first gaming session and a second gaming session. At the first processing slice, a time-sharing processing schedule is determined for the first subset of the online gaming sessions. In accordance with the time-sharing processing schedule, the first and second gaming sessions share a duty cycle of the first processing slice, and are executed dynamically and in parallel according to real-time data processing need of the first and second gaming sessions.

Methods and systems for rendering and encoding content for online interactive gaming sessions

This application is directed to real-time game profiling and analysis. While a game server executes multiple game instances for a gaming title in parallel, a profiling server generates a game profiling instruction to collect data samples associated with a subset of the game instances and sends the game profiling instruction to the game server. In response to the game profiling instruction, the game server identifies the subset of the plurality of game instances, and collects data samples associated with each game instance in the identified subset. Each collected data sample includes at least game state data and system performance data associated with synchronous gaming sessions corresponding to the respective game instance. The game server sends the collected data samples associated with each game instance in the identified subset to the profiling server, which provides the plurality of data samples to an analytics server for further analysis.

Distributed sample-based game profiling with game metadata and metrics and gaming API platform supporting third-party content

An electronic computing system preserves a pre-error state of a processing unit by receiving a first stream of inputs; buffering the first stream of inputs to generate a buffered stream of inputs identical to the first stream of inputs; conveying the first stream to a primary instance of a first program; conveying the buffered stream to a secondary instance of the first program; executing the primary instance on the first stream in real time; executing the secondary instance on the buffered stream with a predefined time delay with respect to execution of the primary instance on the first stream; detecting an error state resulting from execution of the primary instance; and in response to detecting the error state, pausing the secondary instance and preserving a current state of the secondary instance, wherein the current state of the secondary instance corresponds to a pre-error state of the primary instance.

Shadow tracking of real-time interactive simulations for complex system analysis

An electronic game server receives a request from a client device to establish a real-time interactive gaming session, determines a device capability of an output device associated with the client device, determines a connection capability of the network connection, determines one or more target quality parameters for the real-time interactive gaming session based on the device capability and the connection capability, selects a first virtual machine of the plurality of virtual machines based on the one or more target quality parameters, establishes the real-time interactive gaming session with the client device, and provides to the real-time interactive gaming session, in accordance with the resource profile of the first virtual machine, resources for processing inputs from the client device and generating gameplay outputs in accordance with the processed inputs within the real-time interactive gaming session.

Resolution-based scaling of real-time interactive graphics

Methods for partial reconfiguration compatibility detection in an integrated circuit device are disclosed. A disclosed method includes storing a unique identifier that identifies a partial reconfiguration region of the integrated circuit device in a storage circuit. A control circuit may receive an input partial reconfiguration data that activates the operations of the partial reconfiguration region. The method further includes comparing the input partial reconfiguration data to the stored unique identifier prior to activating the operations of the partial reconfiguration region of the integrated circuit device. The input partial reconfiguration data may contain an associated identifier that is derived from the unique identifier during a design compilation operation of the integrated circuit device.

Partial reconfiguration compatibility detection in an integrated circuit device

Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Techniques for compiling and generating a performance analysis for an integrated circuit design

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

This invention provides methods, computer program products, and systems to guide a user in optimizing the Simultaneous Switching Noise (SSN) of an electronic device by using visual approaches on a graphical user interface (GUI). Also provided is an interactive feedback mechanism that enables the user to evaluate the effectiveness of an optimization method. A matrix representation of the different I/O pins on the device shows the level of SSN at different victim pins caused by switching aggressor pins. The SSN is depicted using different graphical representations. Associated with the SSN of each victim pin is the graphical representation of its accuracy. The accuracy rating denotes the reliability of the SSN and is an indication of how sensitive a victim pin is to errors. In the interactive feedback mechanism, user input on SSN optimization is received and used to calculate the new SSN and accuracy rating of different victim pins on the device. The new data is then updated in a timely manner on the GUI.

Simultaneous switching noise optimization

Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.

Pessimism removal in the modeling of simultaneous switching noise

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Toronto, Canada

Paul Leventis