Aquantia Corporation

Marvell Asia Pte., Ltd.

Other

Paul Langner

Ramin Farjadrad

Hossein Sedarat

Ramin Shirani

Kamal Dalmia

Hossein Sederat

Ramin Farjad

Jerry Martinson

George Zimmerman

Saied Benyamin

Simon Edelhaus

Daniel E Voigt

Thomas Wayne Gandy

Tom Gandy

A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

Efficient signaling scheme for high-speed ultra short reach interfaces

A multi-chip module (MCM) includes a first integrated circuit (IC) chip to receive first data. The first IC chip includes a first transfer interface to transmit the first data off the first IC chip. A second IC chip includes an input interface to receive the first data from the first IC chip. The second IC chip includes switching circuitry to selectively forward the first data to one of a first output interface or a second output interface. The first output interface is communicatively coupled to a third IC chip, while the second output interface is configured to output the first data from the MCM.

An Ethernet physical-layer (PHY) device includes an analog front-end and one or more processors. The analog front-end is configured to interface with an Ethernet link that is coupled to a peer Ethernet PHY device. The one or more processors are configured to receive a firmware image from the peer Ethernet PHY device over the Ethernet link, and to boot the Ethernet PHY device and establish Ethernet communication with the peer Ethernet PHY device in accordance with the received firmware image.

Network boot for Ethernet physical-layer devices

A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and, forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits. A symbol mapper modulates the Ethernet block data bits in accordance with an SQ64 constellation comprising back-to-back PAM8 symbols.

High-speed ethernet coding

An Ethernet link is disclosed. The link includes a first Ethernet transceiver and a second Ethernet transceiver configured as a link partner to the first Ethernet transceiver. A shielded twisted quad (STQ) cable is interposed between the first Ethernet transceiver and the second Ethernet transceiver. The STQ cable includes four conductors, each conductor having a first end interfaced with a corresponding input/output (I/O) circuit of the first Ethernet transceiver in a single-ended configuration, and a second end interfaced with a corresponding input/output (I/O) circuit of the second Ethernet transceiver in a single-ended configuration.

Apparatus and method for high-speed ethernet over star quad media

A system including an Ethernet transceiver PHY and a network device is disclosed. The Ethernet transceiver PHY includes register circuitry to store information associated with operating characteristics of the PHY. The network device couples to the Ethernet transceiver PHY in a closed system architecture and includes a system processor and an MDIO interface. The MDIO interface interacts with the PHY register circuitry during a normal operating mode. The system includes system interface circuitry to receive requests for accessing the register circuitry in a debug operating mode. The requests are generated external to the closed system architecture.

Methods and apparatus for PHY register access

An input/output (I/O) interface system for computing devices is disclosed. The I/O interface system includes an externally-engageable USB-C interface connector. A first I/O protocol controller circuit couples to the USB-C interface connector via multiple bidirectional serial lanes. Each of the bidirectional serial lanes transfers a single serial stream of data in a simultaneously bidirectional manner. A second I/O protocol controller circuit couples to the USB-C interface connector via multiple unidirectional serial lanes. Each of the unidirectional serial lanes transfers a single serial stream of data in a unidirectional manner. Mode control circuitry selects between the first I/O protocol controller circuit and the second I/O protocol controller circuit for data transfers with the USB-C interface connector based on a detected signaling media externally connected to the USB-C interface connector.

Apparatus and method for simultaneous bidirectional serial lanes over USB-C interface

A packaged semiconductor device includes a substrate and first, second, and third integrated circuit (IC) chips. The first integrated circuit (IC) chip is mounted on the substrate to receive first data and includes a first transfer interface to transmit the first data via first conductors formed in the substrate. The second IC chip mounts on the substrate and has a second transfer interface to receive the first data. The second IC includes on-chip conductors to route the first data on-chip to an output interface. The output interface transmits the first data via second conductors formed on the substrate. A third IC chip mounts on the substrate and has a third transfer interface to receive the first data via the second conductors.

Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.

Flexible data transmission scheme adaptive to communication channel quality

An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry including transmit circuitry, receive circuitry, and adaptive filters. The transceiver circuitry is configurable to operate in one of two low-power modes. A first low-power mode includes update operations for the adaptive filters. A second low-power mode includes turning off at least one of the transmit circuitry and the receive circuitry, and omitting update operations for the adaptive filters.

Growing community of inventors

Fremont, CA, United States of America

Paul Langner