Cisco Technology, Inc.

Paul Lachlan Mantiply

Straty Argyrakis

Joel Richard Goergen

John Joseph Williams, Jr

Richard Anthony O'Brien

Oded Trainin

Kan Seto

Shobhana Punjabi

Peter Malcolm Barnes

John Joseph Williams

In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.

Integrated power delivery board for delivering power to an ASIC with bypass of signal vias in a printed circuit board

In one embodiment, an apparatus generally comprises a power delivery board for integration with a printed circuit board, the power delivery board comprising a power plane for delivering power from a voltage regulator module to an application specific integrated circuit (ASIC) mounted on a first side of the printed circuit board. The power plane in the power delivery board interconnects with power vias in the power delivery board for vertical alignment with the ASIC through power vias in the printed circuit board to electrically couple the voltage regulator module and the ASIC when the power delivery board is mounted on a second side of the printed circuit board.

Techniques for reducing latency associated with metaframe error correction. Embodiments receive, via a first port of a plurality of ports, a stream of bits within a metaframe. Upon evaluating a first cyclic redundancy check (CRC) for a first portion of the stream of bits and determining that the first CRC is valid, a measure of latency incurred in transmitting the first portion is reduced, relative to first performing forward error correction (FEC) decoding for the first portion prior to transmission, by transmitting the first portion of the stream of bits without performing FEC decoding for the first portion of the stream of bits. Upon evaluating a second CRC for a second portion of the stream of bits and determining that the second CRC is invalid, FEC decoding is performed for the second portion of the stream of bits before forwarding the second portion of the stream of bits.

Minimum latency link layer metaframing and error correction

Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.

Enhanced power distribution to application specific integrated circuits (ASICS)

Embodiments generally provide techniques for data framing and error correction for communications on a link. Embodiments include receiving a stream of bits within a metaframe. Upon determining that a cyclic redundancy check (CRC) for a portion of the stream of bits is valid, the portion of the stream of bits is forwarded without performing forward error correction (FEC) decoding for the first portion. Upon determining that a CRC for the portion of the stream of bits is invalid, FEC decoding is performed for the portion before forwarding the portion of the stream of bits. Embodiments also include generating a metaframe for transmission over a link, and upon determining that a current measure of network throughput is less than a predefined threshold amount of network throughput, inserting one or more checkpoints into the metaframe to create different segments of the metaframe. The metaframe is then transmitted over the link.

A transmission line is provided in which a first portion of the transmission line is configured to be connected to a source, and a second portion of the transmission line is configured to be connected to a load. A capacitive element is coupled to the transmission line and is configured to compensate for an impedance difference between the load and at least one of the source or the transmission line, at a frequency within a frequency bandwidth of the load. A difference between an internal capacitance of the first portion of the transmission line and the second portion of the transmission line substantially matches the capacitance of the capacitive element.

Parasitic capacitance compensating transmission line

A circuit board is provided which includes a plurality of signal pairs of connectors. The signal pairs of connectors are disposed in a triangular grouping of three signal pairs of connectors such that a first connector of each signal pair is located at a vertex of the triangular grouping. A second connector of each signal pair is located at a side of the triangular grouping adjacent to the vertex of the first connector. The signal pairs may be differential pairs.

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Mountain View, CA, United States of America

Paul Lachlan Mantiply