Advanced Micro Devices Corporation

Other

Paul L King

Paul Raymond Besser

Matthew S Buynoski

Eric N Paton

Qi Xiang

John C Foster

Sergey D Lopatin

Minh Van Ngo

Joffre F Bernard

Christy Mei-Chu Woo

Simon Siu-Sing Chan

George Jonathan Kluth

Darin A Chan

Errol Todd Ryan

Amit P Marathe

Jacques J Bertrand

Connie Pin-Chin Wang

Ercan Adem

Robert J Chiu

Jeffrey P Patton

Qi Xang

Thorsten E Kammler

Alexander H Nickel

Austin Frenkel

Susan G Kim

Matthew S Byunoski

Donald Ish

A composite &#x3b1;-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an &#x3b1;-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 &#x212b; to about 50 &#x212b;. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the Nflow rate and/or ratio of the thickness of the combined &#x3b1;-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.

Composite barrier layers with controlled copper interface surface roughness

An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Selectable open circuit and anti-fuse element

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

Conversion of transition metal to silicide through back end processing in integrated circuit technology

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

Reduction of lateral silicide growth in integrated circuit technology

Method of forming composite barrier layers with controlled copper interface surface roughness

A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Selectable open circuit and anti-fuse element, and fabrication method therefor

A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

Low stress sidewall spacer in integrated circuit technology

A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.

Silicide process using high K-dielectrics

The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

Passivation of nitride spacer

A method of reducing electromigration in a dual-inlaid copper interconnect line ( ) by filling a via ( ) with a Cu-rich Cu&mdash;Zn alloy ( ) electroplated on a Cu surface ( from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu&mdash;Zn alloy as fill ( ) for the via ( ) in forming the dual-inlaid interconnect structure ( ). The alloy fill ( ) is formed by electroplating the Cu surface ( ) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill ( ) on the Cu surface ( ); and annealing the electroplated Cu&mdash;Zn alloy fill ( ); and planarizing the Cu&mdash;Zn alloy fill ( ), thereby forming the dual-inlaid copper interconnect line ( ).

Method of reducing electromigration by forming an electroplated copper-zinc interconnect and a semiconductor device thereby formed

A method of reducing electromigration in a graded reduced-oxygen dual-inlaid copper interconnect line by filling a via with a graded Cu-rich Cu&mdash;Zn alloy fill electroplated on a Cu surface using a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a graded reduced-oxygen Cu&mdash;Zn alloy as fill for the via in forming the dual-inlaid interconnect structure. The graded alloy fill is formed by electroplating, while varying electroplating parameters, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the graded fill on the Cu surface; and annealing the electroplated graded Cu&mdash;Zn alloy fill; and planarizing the Cu&mdash;Zn alloy fill, thereby forming the graded reduced-oxygen dual-inlaid copper interconnect line.

Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed

A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu&mdash;Ca&mdash;X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu&mdash;Ca&mdash;X surface, where contaminant X&boxH;C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu&mdash;Ca&mdash;X surface under vacuum onto the underlying Cu interconnect material to form a Cu&mdash;Ca film on Cu interconnect structure, thereby producing a uniform Cu&mdash;Ca film (i.e., Cu-rich with 0.2-5% Ca) on the Cu surface of an interconnect for maximizing Ca&mdash;Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH ) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca&mdash;Cu/Cu interconnect structure.

Method of fabricating a semiconductor device by calcium doping a copper surface using a chemical solution

A semiconductor device having contaminant-reduced calcium-copper (Ca&mdash;Cu) alloy surfaces formed on Cu interconnects fabricated by cost-effectively removing the contaminant layer. Contaminant removal from a Cu&mdash;Ca&mdash;X surface, where contaminant X&boxH;C, S, or O, is achieved by sputtering the Cu&mdash;Ca&mdash;X surface in an argon (Ar) atmosphere between the steps of (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Ca&mdash;Cu alloy surface onto the underlying Cu interconnect material to form a Ca&mdash;Cu/Cu interconnect structure, whereby the sputtering step, under Ar, selectively and effectively removes contaminants from the Cu&mdash;Ca&mdash;X layer containing higher concentrations of C, S, or O, thereby minimizing the post-annealed contaminant level, and thereby producing a uniform Ca&mdash;Cu alloy surface (i.e., Cu-rich with 0.2-5% Ca) on the Cu interconnect material for maximizing Ca&mdash;Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH ) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca&mdash;Cu/Cu interconnect structure.

Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface

A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.

Automated control of metal thickness during film deposition

The present invention is directed to a method of controlling the formation of metal layers. In one illustrative embodiment, the method comprises depositing a layer of metal above a structure, irradiating at least one area of the layer of metal, and analyzing an x-ray spectrum of x-rays leaving the irradiated area to determine a thickness of the layer of metal. In further embodiments of the present invention, a plurality of areas, and in some cases at least five areas, of the layer of metal are irradiated. The layer of metal may be comprised of, for example, titanium, cobalt, nickel, copper, tantalum, etc.

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Mountain View, CA, United States of America

Paul L King