Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Paul L Brohlin

Stephen Christopher Terry

Cetin Kaya

Johan Tjeerd Strydom

Michael Lueders

Deepak Mohanlal Khanchandani

Stephen John Fedigan

Sreenivasan Kalyani Koduri

Christopher Lee Betty

Sandun Shivantha Kuruppu

Steven R Tom

Benjamin Stassen Cook

Erich Bayer

Rajarshi Mukhopadhyay

Sandeep Raj Bahl

Richard Kane Stair

Christophe Vaucourt

Dan Carothers

Trevor Hubbard

Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

Synchronous bootstrap half bridge rectifier

In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

Package for power semiconductor devices

A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.

Probe card for device under test

A device includes a charge controller to regulate a battery output voltage based on an input voltage and an input current received from a charging circuit. A loop controller monitors the input voltage and the input current to generate a feedback signal to adjust the input voltage to the charge controller.

Inductively coupled charger

An embodiment of the invention provides a method for reducing data corruption in a wireless power transmission system. Power is transmitted from a primary coil to a secondary coil by induction. The voltage induced on the secondary coil by induction is rectified. The change in current supplied to a load configured to be coupled to the wireless power transmission system is limited.

Charge control circuitry in a wireless power receiver

One example includes a method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT) that includes at least one GaN transistor device. The method includes inserting the GaN transistor DUT into a test fixture comprising an inductor such that the inductor is coupled to the GaN transistor device to form a switching power regulator. The method also includes operating the switching power regulator at a DUT operating voltage to generate an output current through the inductor based on a DUT input voltage and a duty-cycle. The method also includes controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT. The method also includes measuring the output current and the DUT input voltage at least one of during and after the voltage surge-strike. The method further includes storing the measured output current and the measured DUT input voltage in a memory to specify device characteristics of the GaN transistor DUT.

System and method for surge-testing a gallium nitride transistor device

Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

High low power converter switches, latch, diode isolated intermediate ground

Methods, apparatus, and systems to facilitate high side control of a switching power converter

A motor control circuit includes a processor configured to calculate a plurality of motor impedances from measurements of an excitation voltage on a power bus to a motor and measurements of a plurality of currents through the motor resulting from the excitation voltage, and the processor configured to calculate individual winding inductances in the motor, based on the measured motor impedances, and configured to determine whether there is an inter-turn winding fault based on the calculated individual winding inductances.

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Allen, TX, United States of America

Paul L Brohlin