Arm Limited

Texas Instruments Corporation

Nxp Usa, Inc.

Paul Kimelman

Ian Field

Richard Roy Grisenthwaite

Abhijit Kumar Das

Krishnasawamy Nagaraj

Edmond John Simon Ashfield

Michael John Williams

Andrew Brookfield Swaine

Brian Christopher Kahne

Simon John Craske

David James Seal

Thomas Sean Houlihane

Conrado Blasco Allue

Peter Logan Harrod

Simon Axford

Steven Richard Mellor

Krishnaswamy Nagaraj

Leonardo William Estevez

Franciscus Petrus Widdershoven

Avraham Baum

Adam Fuks

David Francis McHale

Man Cheung Joseph Yiu

Mikel K Ash

Xiaomin Lu

Steven M Meyer

Steve Tuyen Vu

Gary Campbell

Nicholas Esca Smith

Cédric Airaud

Ehud Kalekin

David Aaron Rusling

Jon Andrew Rijk

A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Scalable neural network accelerator architecture

A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

Capacitive sensing

A data processing system includes a processor, a memory, and a cache. The cache includes a cache array, cache control circuitry coupled to receive an access address corresponding to a read access request from the processor and configured to determine whether the received access address hits or misses in the cache array, pre-load control storage circuitry outside the cache array and configured to store a pre-load cache line address and a corresponding stride value, and pre-load control circuitry coupled to the cache control circuit rand the pre-load control storage circuitry. The pre-load control circuitry is configured to receive the access address corresponding to the read access request from the processor and selectively initiating a pre-load from the memory to the cache based on whether a cache line address portion of the access address matches the stored pre-load cache line address.

Cache pre-loading in a data processing system

In a data processing system having a local first level cache which covers an address range of a backing store, a distributed second level cache has a plurality of distributed cache portions, each assigned as a home cache portion for a corresponding non-overlapping address sub-range of the address range of the backing store. Upon receipt of a read access request to a read-only address location of the backing store, the local first level cache is configured to, when the read-only address location misses in the local first level cache, send the read access request to a most local distributed cache portion of the plurality of distributed cache portions for the local first level cache to determine whether the read-only access location hits or misses in the most local distributed cache portion, in which the most local distributed cache portion is not the home cache portion for the read-only address location.

Data processing system implemented having a distributed cache

A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.

Data processing system having a shared cache

A data processing system including a cache operably coupled to an interconnect and a cache controller. The cache is accessible by each bus initiator of a plurality of bus initiators. The cache includes a plurality of entries. Each entry includes a status field having coherency bits. When an entry of the plurality of entries is in a first protocol mode, the cache controller uses the coherency bits of the entry in implementing a first cache coherency protocol for data of the entry. When the entry is in a second protocol mode, the cache controller uses the coherency bits of the entry in implementing a second cache coherency protocol. The second cache coherency protocol is utilized in implementing a paced data transfer operation between a first bus initiator of the plurality of bus initiators and a second bus initiator of the plurality of bus initiators using the cache entry.

Producer/consumer paced data transfer within a data processing system having a cache which implements different cache coherency protocols

A system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.

Glitch detection in input/output bus

A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

A method for automation and control of a wireless device in a WiFi environment. The method includes a wireless mobile device configured with a soft access point (softAP) transmitting probe requests to home automation devices and traditional stationary access points. The wireless mobile device periodically wakes up to scan for other services, sends a probe request, authenticates the received probe response from the another device and receives control information via the received probe response.

Power efficient method for Wi-Fi home automation

Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.

Circuits and methods for determining the temperature of a transistor

A secure environment is established within a system on a chip (SoC) without the use of a memory management unit. A set of security parameters is produced by a configuration program executed by a processor within the SoC that is read from a first non-volatile memory within the SoC. A set of stored parameters is created in a committable non-volatile memory within the SoC by writing the set of security parameters into the committable non-volatile memory. The committable non-volatile memory is sealed so that that it cannot be read or written by the processor after being sealed. The stored parameters can then be accessed only by control circuitry. Security circuitry within the SoC is configured using the stored parameters each time the SoC is initialized and thereby enforces the secure environment within the SoC.

Microcontroller with embedded secure feature

A system comprises an enclosure, host logic contained in the enclosure, and intrusion security logic also contained in the enclosure. The intrusion security logic is coupled to the host logic and configured to detect a security intrusion to the system and to respond to a security intrusion with a user-configurable trigger event. The intrusion security logic implements at least two tamper blocks, each tamper block configured to monitor one more input signals and initiate a trigger event when a security breach of the enclosure is detected. At least one of the tamper blocks comprises a state machine whose operation is controlled by way of user-programmable registers.

Growing community of inventors

Alamo, CA, United States of America

Paul Kimelman