Fungible, Inc.

Juniper Networks, Inc.

Nvidia Corporation

Fortinet, Inc.

Cisco Technology, Inc.

Innovium, Inc.

Microsoft Technology Licensing, LLC

Altera Corporation

Paul Kim

Wael Noureddine

Jean-Marc Frailong

Deepak Goel

Felix A Marti

Zahid S Hussain

Tim Millet

Sachin Desai

Louise Y Yeung

Ken Yeung

Edward Anthony Hutchins

Charles Edward Gray

Pradeep S Sindhu

Bertrand Serlet

Gary S Goldman

Brian K Angell

Puneet Agarwal

Rajan Goyal

William Brad Matthews

Aibing Zhou

Robert Rhoades

Mugdha G Patil

Bruce Hui Kwan

Philip A Thomas

Gary Brian Wallichs

Chang-Hong Wu

Yi Peng

NischalKumar N Sheth

Jim Battle

Alfredo De La Cruz

Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Efficient work unit processing in a multicore system

A method during a first cycle includes receiving, at a first port of a device, a plurality of network packets. The method may include storing, by the device, at least some portion of a first packet of the plurality of network packets at a first address within a first record bank and storing, by the device and concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank. The method may further include storing, by the device, the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank and updating, by the device, a tail pointer to reference the second address.

Efficient packet queueing for computer networks

An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Access node for data centers

A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.

Access node integrated circuit for data centers which includes a networking unit, a plurality of host units, processing clusters, a data network fabric, and a control network fabric

Approaches, techniques, and mechanisms are disclosed for improving the efficiency with which data units are handled within a device, such as a networking device. Received data units, or portions thereof, are temporarily stored within one or more memories of a merging component, while the merging component waits to receive control information for the data units. Once received, the merging component merges the control information with the associated data units. The merging component dispatches the merged data units, or portions thereof, to an interconnect component, which forwards the merged data units to destinations indicated by the control information. The device is configured to intelligently schedule the dispatching of merged data units to the interconnect component. To this end, the device includes a scheduler configured to select which merged data units to dispatch at which times based on a variety of factors described herein.

Scalable ingress arbitration for merging control and payload

Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

Integrated circuits having expandable processor memory

A token bucket or leaky bucket is maintained at least partially through the use of two separate counters. A full counter, is maintained in relatively lower cost memory, and indicates the amount of tokens within the bucket on a potentially delayed basis. An intermediate counter is stored in a relatively higher cost memory that supports high access rates, and indicates the amount of tokens assigned (or unassigned) to the bucket since the full counter was last updated. Various adjustment processes remove (or add) tokens as needed for performing tasks. A background process updates the full counter from the corresponding intermediate counter on a periodic, scheduled, or other basis. The buckets are replenished (or deleted) with tokens periodically at assigned rates. Traffic management or other decisions are based on the bucket's current status, as determined from the full counter during the background process and then stored in the higher cost memory.

Efficient traffic management

Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory.

Buffer allocation and memory management

Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory. The mapping table may include one or more entries organized in a tree structure.

Buffer allocation and memory management using mapping table

A device may receive a packet that includes a destination address. The device may analyze a first Bloom filter, based on the destination address, in order to identify a prefix range entry associated with the destination address and included in a set of prefix range entries associated with the first Bloom filter. The device may analyze a second Bloom filter, based on the destination address and the identified prefix range entry, in order to identify a prefix length entry associated with the destination address and included in a set of prefix length entries associated with the second Bloom filter. The device may determine routing information associated with the identified prefix length entry. The routing information may identify a longest prefix match associated with the destination address. The device may provide the packet based on the routing information.

Two stage bloom filter for longest prefix match

A device may receive a packet with a destination address, and may input, to a probabilistic filter, prefixes associated with the destination address. A prefix may include one or more most significant bits of the destination address. The device may identify candidate prefixes associated with a response from the probabilistic filter. The device may identify a longest candidate prefix of the candidate prefixes, and may perform a lookup to determine that a memory component includes a parent prefix that matches the longest candidate prefix. The parent prefix may be associated with a child prefixes that include the parent prefix and one or more additional bits. The device may identify a longest matching prefix, of the parent prefix and the child prefixes, that matches one or more most significant bits of the destination address and that corresponds to an output component. The device may output the packet via the output component.

Forwarding packets using a probabilistic filter and a grouping technique

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Fremont, CA, United States of America

Paul Kim