Agilent Technologies, Inc.

Paul Keltcher

Jeanne M Hermsen

A size configurable data buffer includes a plurality of data cache memory registers and a variable number of prefetch memory registers. A computer controller determines the allocation of the data buffer which is data cache memory registers or prefetch memory registers. The size configurable data buffer may be included within a single size configurable data buffer SRAM circuit.

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Cupertino, CA, United States of America

Paul Keltcher