Prime Computer Inc.

Paul K Rodman

Joseph L Ardini, Jr

Brian Lefsky

Robert F Beckwith

David B Papworth

Stephen S Corbin

Chi-Ping Chen

A data processing system, wherein the central processing unit has an arithmetic element for processing data in response to machine program instructions and a control store for microcode program storage responsive to the machine instructions for implementing the instruction, has an improved arithmetic unit for enabling higher throughput without substantially increasing hardware cost. The arithmetic unit has a reconfigurable arithmetic logic unit which is controlled in response to both hardware generated data signals and microcode generated data signals. A data string manipulation circuitry provides for aligning data strings for processing by the arithmetic logic unit. Circuitry is provided, responsive to a decoded machine instruction, for generating control signals for configuring the arithmetic unit and for controlling the data string manipulation circuitry. As a result, the number of microcode steps needed to implement particular decimal and string manipulation machine instructions is significantly reduced, thereby saving machine cycles, while the additional hardware cost is very modest.

Data processing system and method having an improved arithmetic unit

A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

Memory alignment system and method

A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjuction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents. Each element of the list defines one of those cache storage locations and also identifies the location in the CIT memory of the next element in the list.

Multiprocessor cache coherence system

An address translation method and apparatus is disclosed for use in an auxiliary memory of a computer, which stores data in association with a tag defining its location in a main memory, and also includes a buffer for storing a plurality of addresses together with translations of the corresponding main memory locations, permitting data obtained from the auxiliary memory to be validated by comparing the tag with the translation from the buffer. An improvement in the auxiliary memory is disclosed consisting of a content addressable memory (CAM) for storing translations not found in the buffer. The CAM is adapted so that it can be searched for a translation and the translation, if found in the CAM, is employed to verify data in the auxiliary memory.

Address translation systems for high speed computer memories

A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

Growing community of inventors

Ashland, MA, United States of America

Paul K Rodman