Link a Media Devices Corporation

Etopus Technology Inc.

Lsi Logic Corporation

Sk Hynix Memory Solutions Inc.

Paul K Lai

Kwok Wah Yeung

Kai Keung Chan

Danfeng Xu

Shirish A Altekar

Kwok Alfred Yeung

Xin-Ning Song

Tze Yin Cheung

Xiaolong Liu

Hon Man Yau

A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.

Configurable transmitter device based on data rate

A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.

Clock duty cycle calibration and phase calibration for high-speed transmitter

Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.

Pad bit injection during read operation to improve format efficiency

A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.

Low power viterbi trace back architecture

Structure and methods for reduced latency in calculating an error signal based on the output of a Viterbi detector. Certain partial terms of the error signal are precomputed before the final output of the Viterbi detector is determined. The precomputed terms are used to determine the error in fewer clock cycles once the Viterbi output is fully determined. In one exemplary embodiment, the final Viterbi output is used as an input to a multiplexer that selects a precomputed error. In addition to calculating an error signal, a level signal may be precomputed as well so that the level signal is available more quickly after the output of the Viterbi detector is fully determined.

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San Jose, CA, United States of America

Paul K Lai