Integrated Device Technology, Inc.

Paul Joseph Murtagh

Alejandro F Gonzalez

Prashant Shamarao

Roland T Knaack

Declan McDonagh

A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

DRAM interface circuits that support fast deskew calibration and methods of operating same

Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

DRAM interface circuits having enhanced skew, slew rate and impedance control

A phase locked loop (PLL) circuit includes a controlled oscillator circuit that is operative to generate an output clock signal responsive to an oscillator control signal according to a plurality of selectable transfer functions, and an oscillator control signal generator circuit that is operative to generate the oscillator control signal responsive to the output clock signal and a reference clock signal. The PLL circuit further includes a transfer function control circuit operative to transition operation of the controlled oscillator from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control signal. For example, the transfer function control circuit may step the controlled oscillator circuit through a succession of the transfer functions in response to a change in a frequency of the reference clock signal and may enable a closed loop including the oscillator control signal generator circuit and the controlled oscillator circuit upon selection of each of the succession of transfer functions.

Dynamic phase-locked loop circuits and methods of operation thereof

Delay-locked loops have high bandwidth locking characteristics that are less susceptible process, voltage and temperature (PVT) variations. These DLLs are configured to support transition from a partial feedback loop lock condition to a full feedback loop lock condition during a start-up time interval, in order to insure that a multi-cycle lock condition is established at the time the DLL's clock signal output becomes available. The DLL may include a variable delay line that is responsive to a reference clock signal, an auxiliary phase detector that is electrically coupled to the variable delay line, and a main phase detector that is responsive to the reference clock signal and a feedback clock signal (DLLCLK). The auxiliary phase detector may be an edge-triggered SR-type phase detector and the main phase detector may be a three-state phase frequency detector.

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Duluth, GA, United States of America

Paul Joseph Murtagh