International Business Machines Corporation

Paul Joseph Milot

James Anthony Pafumi

Leslie Robert Wilson

Marc Segre

Robert Paul Stelzer

Gary Bischoff

Jeffrey S Spencer

A computer system having a graphics display with texture management employs a graphics adapter with texture memory. The graphics adapter is 'virtualized' by the operating system. When making a graphics context switch, the state of the graphics adapter including texture memory is saved. Threads are used to allow rapid and frequent context switches. A graphics process that will use texture memory in the adapter reserves a thread, for use during a graphics context switch. The thread calls into the operating system where it is blocked until a graphics context switch is initiated. At that time, the thread is unblocked to do texture management, such as saving of texture memory. During the save portion of the graphics context switch the graphics driver saves the current hardware state of the adapter, and the special purpose texture thread is unblocked to allow texture memory to be processed, and saves texture memory and calls back into the driver where it is blocked. During the restore portion of the graphics context switch the driver restores the state of the adapter to that of another graphics process, except for texture memory. The special purpose texture thread associated with the new graphics process is unblocked, passed an indication that a restore operation is in progress, and restores textures as required and calls back into the driver where it is blocked in the kernel. The driver completes the context switch and the graphics process is dispatched.

Synchronizing graphics texture management in a computer system using threads

Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.

Bidirectional FIFO buffer for interfacing between two buses of a

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Paul Joseph Milot