Sun Microsystems, Inc.

International Business Machines Corporation

Oracle International Corporation

Oracle America, Inc.

Sambanova Systems, Inc.

Syrus Ziai

Paul Joseph Jordan

Gregory Frederick Grohoski

Manish K Shah

Robert T Golla

Hung Qui Le

Mark Luttrell

Christopher Hans Olson

Hoichi Cheong

Ali Vahidsafa

James Ray Lewis

Jama Ismail Barreh

Gregory Charles Onufer

Jeffrey S Brooks

Ashley N Saulsbury

Rabin Sugumar

Michael Stephen Floyd

Peter Juergen Klim

Steven Wayne White

Yuan C Chou

Fong Pong

John Johnson

Zoran Radovic

Matthew B Smittle

Zeid Hartuon Samoail

Leslie D Kohn

Quinn Able Jacobson

Lee Evan Eisen

Kevin Franklin Reick

Dawei Huang

Michael D Snyder

Alexander Erik Mericas

Soummya Mallick

Kurt Alan Feiste

Paul N Loewenstein

Ricky C Hetherington

Brian R Konigsburg

Michael K Wong

Nicolai Kosche

Ravinder Kumar

John D Pape

Larry Scott Leitner

Tung M Nguyen

John Edward Derrick

Mark Debbage

Joel Roger Davidson

Thomas Alan Ziaja

Graham Ricketson Murphy

Ryan Patrick Donohue

Gregory F Grohoski

Jared Smolens

Oscar R Mitchell

Robert M Maier

Emre Ali Burhan

Nathan Francis Sheeley

William R Hardell, Jr

Maran Wilson

Robert William Hay

Jared C Smolens

Craig Robson

Judith E K Laurens

William J Kucharski

Quan Nguyen

Greg F Grohoski

Greg Grohoski

Yue Chang

Venkatesh Iyengar

Roman Zajcew

Joseph T Rahmeh

Jike Chong

Mark Greenberg

Tung Manh Nguyen

Yonjae Rim

Yong Qin

Munsefar Khaleque

Gregory Onufer

Al Chang

A Coarse-grained Reconfigurable Processor (CGRP) includes an internal network with request, response, and data networks operating concurrently as separate packet-switched networks. The CGRP includes external interface circuits coupled to an interface configurable unit in an array of configurable units through the internal network. The CGRP also includes a network health monitor circuit that is configured to detect network failure conditions by writing and then reading health monitor registers across the internal network.

Network health monitor within a coarse grained reconfigurable architecture processor

A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.

Handling interrupts from a virtual function in a system with a reconfigurable processor

An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Method for migrating CPU state from an inoperable core to a spare core

A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.

Peer-to-peer route through in a reconfigurable computing system

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

Scannable memory array and a method for scanning memory

A processor has multiple memory interfaces and a memory interleaver controlling access to the memory interfaces. The memory interfaces may each couple with one or more memory devices. The number of memory devices coupled to the different memory interfaces may be unequal. The memory interleaver determines a memory region from a logical address, and a region relative address. It determines the interleave factor IF corresponding to the memory region. It performs an integer division to obtain a device line address, and a modulo operation to obtain an uncorrected channel address. The memory interleaver may add a region start address associated with the memory region to the device line address to obtain a physical line address. It may correct the uncorrected channel address, based on the memory region, to obtain a physical channel address. Some implementations use configuration memories to allow flexibility, other implementations are hardwired for a particular memory architecture.

Non-uniform memory interleaving processor

A method to access memory in a physical memory space includes receiving a logical line address (LLA) from a processor, converting the LLA to a physical line address (PLA) and a physical channel address (PCA), and accessing the memory using the PLA and PCA. The memory has multiple memory channels, and multiple memory regions. A memory device may occupy an intersection of a memory region and a memory channel. The conversion includes determining the memory region from the LLA, and determining a region relative address (RRA) from the LLA. The method determines an interleave factor (IF) from the region, and a device line address (DLA) and an uncorrected channel address (UCA) from the RRA and the IF. The method determines the PLA from the DLA and the memory region, and it determines the PCA from the UCA and the memory region.

Non-uniform memory interleave method

An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.

Hardware mechanism to mitigate stalling of a processor core

Random numbers within a processor may be scarce, especially when multiple hardware threads are consuming them. A local random number buffer can be used by an execution core to better manage allocation and consumption of random numbers. The buffer may operate in a number of modes, and allow any hardware thread to use a random number under some conditions. In other conditions, only certain hardware threads may be allowed to consume a random number. The local random number buffer may have a dynamic pool of entries usable by any hardware thread, as well as reserved entries usable by only particular hardware threads. Further, a user-level instruction is disclosed that can be stored in a wait queue in response to a random number being unavailable, rather than having the instruction's request for a random number simply be denied. The random number buffer may also boost performance and reduce latency.

Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of cores

Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.

Load-monitor mwait

Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.

Precise excecution of versioned store instructions

Growing community of inventors

Austin, TX, United States of America

Paul Joseph Jordan