Hewlett-packard Development Company, L.p.

Paul John Mantey

Michael John Erickson

David R Maciorowski

John S Atkinson

Mike J Erickson

Michael D Young

Russ William Herrell

Bradley Dean Winick

Daniel V Zilavy

Wallace K Johnson

Danial V Zilavy

Michael Ryan Davis

David R Macior Wski

A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.

Communications bus transceiver

A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Apparatus and method for selectively mapping proper boot image to processors of heterogeneous computer systems

Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Detecting and diagnosing a malfunctioning host coupled to a communications bus

A computer system has at least one processor, a memory system, a Joint Test Action Group (JTAG) bus interface, and Input/Ouput devices. At least one Input/Ouput device of the system has an integrated circuit connected to and readable by the JTAG bus interface. The memory system of the computer system contains an exception handler capable of reading a state of the readable integrated circuit of the Input/Output device upon occurrence of an exception.

Apparatus and method for saving precise system state following exceptions

Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Systems and methods for accessing bus-mastered system resources

Systems, methods and software products ensure correct connectivity between circuit designs. A list of connections of the circuit designs is generated. One or more mapping files are generated from the list to correlate connections between the circuit designs. The mapping file is regenerated in response to modification of at least one of the circuit designs. Optionally, at least one schematic associated with at least one of the circuit designs is regenerated using information in the regenerated mapping file

Systems and methods for ensuring correct connectivity between circuit designs

A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.

System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system

A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

Computer system with multiple backup management processors for handling embedded processor failure

A field unit has a connector with first and second interconnect apparatus coupled to connector. The field replaceable unit has test apparatus coupled to the first and second interconnect apparatus capable of testing connections through the connector to the first interconnect apparatus under control of signals on the second interconnect apparatus. The field replaceable unit is capable of being hot-plugged. In an embodiment, the second interconnect apparatus is of the JTAG type. Also claimed is a method of testing interconnect between the field replaceable unit and another unit of a system into which it has been hot-plugged.

Apparatus and method for verification of system interconnect upon hot-plugging of electronic field replaceable units

The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

System for ensuring correct pin assignments between system board connections using common mapping files

A system for removal and replacement of core I/O devices while the rest of the computer system is powered-up and operational. The system comprises a custom form-factor core I/O card that contains a plurality of I/O devices, including a processor for managing the card's I/O functions. A command is sent to an operating system, running on a system processor external to the core I/O card, that notifies the system to stop using, and de-configure, the hardware on the core I/O card. Once the OS receives this notification, an indication that the card is ready to be removed is sent to the user. The user then removes the card from its slot and inserts a replacement card into the same slot. The system software then discovers the I/O components on the core I/O card to determine what components are available, and then configures the new I/O device(s).

System for removing and replacing core I/O hardware in an operational computer system

Method for ensuring correct pin assignments between system board connections using common mapping files

An electrical connector assembly has a flexible circuit with a first end portion, a second end portion, a first surface, and a second surface. A plurality of conductors extend between the first end portion and the second end portion within the circuit. A first connector assembly is attached to the circuit first end portion. The first connector assembly has a first connector electrically connected to at least one of the plurality of conductors, a first plate substantially encompassing the first connector and located adjacent the circuit first surface, and a second plate located adjacent the circuit second surface and opposite the first plate. The first plate and the second plate are mechanically coupled.

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Fort Collins, CO, United States of America

Paul John Mantey