International Business Machines Corporation

Paul Jacob Logsdon

Franco Motika

Richard Frank Rizzolo

Sean Michael Carey

Christian Jacobi

Chung-Lung K Shum

Alper Buyuktosunoglu

Anthony Saporito

William Vincent Huott

Mary Prilotski Kusko

Adam B Collura

Tobias Webel

Michael J Cadigan, Jr

Stefan Payer

Andrew A Turner

Bodo Hoppe

Eugene R Atwood

Pawel Owczarczyk

Divya Kumudprakash Joshi

Karl Evan Smock Anderson

Michael Romain

Sreekala Anandavally

Mark Cichanowski

William Rurik

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests ('LBIST') trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Error injection for timing margin protection and frequency closure

Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.

Empirical LBIST latch switching and state probability determination

Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.

Optimizing generation of test configurations for built-in self-testing

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Poughkeepsie, NY, United States of America

Paul Jacob Logsdon