Micron Technology Incorporated

Paul J Voit

Travis E Swanson

Ryan M Przybilla

Jeffrey R Jobs

Ryan M Przbilla

The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.

Channel skewing

Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.

A computer system having a primary serial bus and one or more serial sub-busses separated from the primary serial bus by gating devices is described. By selectively enabling different gating devices (thereby coupling one serial sub-bus to the primary serial bus at a time), each sub-bus may support the maximum number of addressable devices. This, in turn, expands the effective serial bus address space of the computer system.

Mechanism to expand address space of a serial bus

An improved computer clock circuit capable of automatically detecting the internal clock frequency of a peripheral component installed in a peripheral component interconnect (PCI) slot, and supplying the PCI slot with the a clock signal of a specified frequency. In one embodiment, the clock circuit comprises a reference clock generator having multiple clock frequencies, a phaselocked loop (PLL) based clock driver, and circuitry providing the clock driver with a selection signal indicative of the configuration of a component connected within a PCI slot. The PLL clock driver maintains phase coherency between the input and output signals, thereby reducing setup and hold times within the system and peripheral components. Additionally, the PLL clock driver reduces propagation delays within the clock circuitry, and greatly simplifies implementation of the clock circuit within a given design. In another embodiment of the invention, the clock driver is also used to generate clock signals having a predetermined relationship to those produced by the reference generator, in addition to the clock signal supplied to the PCI slot. A method of automatically selecting and providing a desired clock frequency to a PCI slot is also disclosed.

Apparatus and method for automatically selecting an appropriate signal from a plurality of signals, based on the configuration of a peripheral installed within a computing device

A system has one or more electronic devices and ports adapted to be coupled to the one or more electronic devices. Voltage regulators are each coupled to provide a voltage signal to a corresponding port. A decoder is coupled to the ports to detect if one of the ports is not coupled to an electronic device and to enable system operation even though one of the ports is not coupled to an electronic device and the voltage signal provided to the one port is not at a predetermined level.

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Ham Lake, MN, United States of America

Paul J Voit