International Business Machines Corporation

Paul J Tsang

Narasipur G Anantha

Louis L Hsu

Seiki Ogura

Joseph F Shepard

Jacob Riseman

Victor J Silvestri

Cheng Tzong Horng

John Anthony Fitzsimmons

Roy Arthur Carruthers

Robert Otto Schwenker

Geraldine C Schwartz

San-Mei Ku

Fernand J Dorleans

Gerald R Larsen

James A Jubinsky

Richard Flitsch

Robert W Zielinski

Tak H Ning

Jonathan Daniel Chapple-Sokol

Santosh Prasad Gaur

Michael R Poponiak

Chi-Min Yuan

Russell C Lange

Shao-Fu S Chu

Richard A Gilmour

Wen-Yuan Wang

Ven Y Doo

Yi-Shiou Huang

Kerry L Batdorf

John L Deines

Joseph F Shephard

Donald P Cameron

A subtractive method for making a Levenson type lithographic phase shift mask using a sacrificial etch monitor film in which some of the monitor film is left standing on the opaque portions of the mask. The monitor film otherwise is consumed when it is simultaneously etched with selected portions of the mask substrate to produce recesses of desired depth in the substrate. The etching is stopped upon detecting that the etched monitor film is completely consumed. The technique also is adapted for the fabrication of a RIM type lithographic phase shift mask combined with the Levenson type phase shift mask in the same mask. The technique further is adapted to include 90 degree shift transitions at the end of the Levenson line-space pairs of the mask. The monitor film left standing on the opaque portions of the mask provides self-aligned phase error correction to offset sidewall scattering in the Levenson type mask.

Dual phase and hybrid phase shifting mask fabrication using a surface

A method of fabricating a microfuse, deletable by laser pulses utilizes laser pulses of a predetermined spot diameter and beam alignment accuracy. A fusible link forming a portion of the microfuse is defined such that its length is at least equal to the sum of the laser spot diameter and the beam alignment accuracy and its width is no greater than half the laser spot diameter. A method of deleting the microfuse by laser pulses is provided where the microfuse has a predetermined composition, length and width having an axis bisecting the width and parallel to the length and is covered with a passivation layer at least 3 .mu.m thick. The method includes adjusting the diameter of the beam of laser light (i) to at least a minimum diameter of W+.DELTA.P.sub.w, where W equals the width of the microfuse fuse link and .DELTA. P.sub.w equals the accuracy of the beam in the direction of W and (ii) to no more than a maximum diameter of L+.DELTA.P.sub.L, where L equals the length of the microfuse fuse link and .DELTA.P.sub.L equals the accuracy of the beam in the direction of L.

Fabrication and laser deletion of microfuses

A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Structure and fabrication of SiCr microfuses

SiCr microfuses

A lightly doped drain, field effect transistor with an inverted 'T'-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

Inverse T-gate FET transistor with lightly doped source and drain region

A method of forming an LDD field effect transistor with an inverted 'T'-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

Method of forming an inverse T-gate FET transistor

A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

Process of making BiCMOS devices having closely spaced device regions

A novel method of employing selective epitaxial growth, in which interdevice isolation is intrinsically formed. Problems stemming from formation of all active device elements within selective epitaxial growth regions are addressed. Additionally, there is shown a novel transistor array formed according to the method of the invention.

Fabrication of dielectrically isolated integrated circuit devices

Selective epitaxial growth structure and isolation

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Fabrication methods for high performance lateral bipolar transistors

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ buried layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base a insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first mask to partially cover the collector. At the same time that the NPN extrinsic base contact is made, P-type dopants are introduced in the areas exposed by the first and second masks to provide an emitter and a collector contact for the PNP transistor.

Method of fabricating a lateral PNP transistor

A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove. The P+ polycrystalline silicon layer is then formed on the surface which will in turn fill the groove with this material. The heating of the structure forms the P+ emitter region around the side edges of the P+ polycrystalline silicon filled groove. The P+ polycrystalline layer is the emitter contact, the N+ reach-through connected through the buried N+ region is the base contact and the collector contact is made to the P-type collector region.

Methods for making high performance lateral bipolar transistors

A transistor and method of forming the same are disclosed. A thick mesa of dielectric material is grown on a semiconductor substrate and two or more layers of polycrystalline silicon grown on the vertical sides of the mesa serve a masking function to define the gate region of the transistor with high accuracy. The mesa and the two or more polycrystalline layers remain in the final device.

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Poughkeepsie, NY, United States of America

Paul J Tsang