Altera Corporation

Paul J Tracy

Adam J Wright

Jayabrata Ghosh Dastidar

Michael Harms

Andy Louie Lee

Steven Perry

Rahul Saini

Hung Hing Anthony Pang

Binh Vo

Ajay Nagarandal

Dhananjay Srinivasa Raghavan

John DiCosola

Anthony Pang

Balaji Natarajan

Eric C Chang

Mandrita Brahmachari

Techniques are provided that control the generation of test routes to improve the ability of a test system to isolate defects on programmable circuits. A test generator creates test routes that test the horizontal resources. In these test routes, the inputs of each circuit element are only connected to other circuit elements in the same row. Test routes are also generated to test the vertical resources. Each of theses test routes is allowed to make only one transition from between two different rows of circuit elements. The configuration generator includes a post processor that ensures all source drivers in the test routes connect to at least two sinks.

Automatic test configuration generation facilitating repair of programmable circuits

The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i.e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.

Method of maintaining signal integrity across a capacitive coupled solder bump

An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associated features such as a weak pull-up feature, a voltage clamp diode feature, a bus hold feature, an open-drain feature, a differential input termination resistance feature, and a single-ended/differential mode selection feature. An input-output feature control register receives input-output circuit feature selection instructions. The feature selection instructions contain feature selection bits whose values determine which of the input-output circuit features are enabled in a set of input-output circuits for testing on the integrated circuit. The feature selection instructions can selectively enable one or more input-output circuit features in each input-output circuit. Different feature selection instructions can be loaded into the feature control register to systematically test the input-output circuit features.

Feature control circuitry for testing integrated circuits

A programmable device with an improved system for loading configuration data compresses configuration data by composing configuration data out of pairs of control words and data words. The configuration data is divided into configuration words. Each configuration word is further divided into a number of configuration blocks. In a control word/data word pair, the control word determines which configuration blocks in the configuration word will be loaded with the data word. Each configuration block designated by the control word will be simultaneously loaded with the data word. By taking advantage of the symmetry within the control word, typically only a small number of control word/data word pairs will be required to load a complete control word. If a given control word does not have sufficient symmetry, the programmable device can instead use an alternate system for loading the configuration word.

System for loading configuration data into a configuration word register by independently loading a plurality of configuration blocks through a plurality of configuration inputs

A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.

Method and apparatus for testing interconnect bridging faults in an FPGA

Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application is identified. A test is then performed only on the set and a test result is generated. Defective resources may be replaced. The PLD is identified as defective only if one of the resources associated with the customer application is defective. Such application specific testing allows the ability of the customer to perform in-system testing, the reduction of the time required for testing the PLD, and the testing of PLDs based on knowledge of the customer's application, among other advantages.

Method and apparatus for application specific test of PLDs

Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.

Techniques for automatically generating tests for programmable circuits

Circuits, methods, and apparatus for output response analyzers that may be used during integrated circuit testing. Current output test data is compared with previous output test data. In this way, repetitive test patterns such as checkerboards may be employed while limiting circuit complexity. The outputs of several built-in self-test circuits may be combined into as few as one signal that may be provided as a test output.

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Sunnyvale, CA, United States of America

Paul J Tracy