Advanced Micro Devices Corporation

Other

Paul J Steffan

Allen S Yu

Ming Chun Chen

Thomas C Scholer

Jeffrey P Erhardt

Patrick K Cheung

Shivananda S Shetty

Bharath Rangarajan

John JianShi Wang

Franklyn Shihyu Wu

David C Newbury

Jian Feng Chen

Hsingya Arthur Wang

Michael G McIntyre

Bryan M Tracy

Srikanth Sundararajan

Siu May Ho

Steven J Zika

Chau M Ho

Charlie Reading

Jerry H G Tsiang

An image processing system provides a method for processing an image including classifying the image, comparing the image to stored images, storing the image if the image does not match one of the stored images, and storing a link to a stored image if the image matches one of the stored images.

Image processing in integrated circuit technology development

A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.

Method and apparatus for correlating semiconductor process data with known prior process data

A method for facilitating semiconductor wafer lot disposition includes providing detailed descriptive information of the semiconductor wafer layout and generating data concerning at least one defect in the semiconductor wafers at an intermediate processing stage. At least one layer model is generated from the information and data to disclose the effects of the defect upon at least one later layer of the semiconductor wafers. The layer model is utilized to determine the subsequent disposition of the wafer lot.

Predicting defect future effects in integrated circuit technology development to facilitate semiconductor wafer lot disposition

A method for failure analysis of small contacts in integrated circuits is provided. A number of opposing electrical contacts is configured to contact a sample in an offset pattern such that any one electrical contact may contact more than one conductor in the sample and any opposing electrical contact is offset-positioned to contact no more than one of the conductors contacted by the one electrical contact.

Test structure and method for failure analysis of small contacts in integrated circuit technology development

A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.

Wafer level global bitmap characterization in integrated circuit technology development

A method and system of processing tester information of a system under test is provided. Data of a tested characteristic of the system under test is generated. A distribution curve is extracted from the data. A signature of the distribution curve is determined, and a map of the signature on a depiction of the system under test is presented. The distribution curve also can be categorized in a plurality of bins, and bitmaps are generated for the sections in each of the plurality of bins. Systematic signatures are determined from the bitmaps in the block, and the signatures are correlated with the locations on the system under test.

Characterizing distribution signatures in integrated circuit technology

A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.

Testing multiple levels in integrated circuit technology development

A method of manufacturing a semiconductor device with a reduced bit-line isolation dimension. After a layer of image sensitive photoresist is patterned and developed with openings having the minimum printable dimension, the layer of photoresist is silylated causing the layer of photoresist to swell, which causes the opening dimension to decrease.

Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices

An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Controlled gate length and gate profile semiconductor device and manufacturing method therefor

A method of analyzing defect images in a semiconductor manufacturing process wherein descriptors are assigned to images of defects caught during scanning of an inspection wafer. The images, assigned descriptors and linkage data are stored in a relational database. An operator can select an image to analyze and the review station assigns descriptors to the selected image and the database is searched for images having the assigned descriptors.

Composition based association engine for image archival systems

Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having channels length less than that available from standard photolithographic methods of forming gates and channels.

Method of forming low resistance reduced channel length transistors

A method of reducing the effect of placement errors during defect capture and analysis during the manufacture of integrated devices on semiconductor wafers wherein defects from a current layer are evaluated in relation to defects from previous layers after an oversized overlay map has been utilized to perform a best-fit analysis of current defects and previous defects, the oversized overlay map reduced and a trend analysis performed to determine error type and the coordinates of defects translated to their proper location.

Overlay radius offset shift engine

A method of analyzing and classifying defects on a semiconductor wafer during a semiconductor manufacturing process using an automatic defect resizing tool to accurately measure the sizes of defects.

Automatic defect resizing tool

A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.

Semiconductor with increased gate coupling coefficient

Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.

Growing community of inventors

Elk Grove, CA, United States of America

Paul J Steffan