Innovasic, Inc.

Honeywell G.m.b.h.

Quadric, Inc.

Stc.unm

Paul J Short

Taylor M Wray

Thomas A Weingartner

William Broome

Dean J Arriens

Plamen B Atanassov

William Ray Hancock

Alexey Serov

Andrew David Alsup

Barr Halevi

Jennifer A Graves

Jordon W Woods

Mark A Espelien

Paul E Knight

The present invention relates primarily to craft beer, specifically the creation of a method to create flavorful non-alcoholic and low-alcoholic versions of virtually any style of craft beer. It also relates to craft distilled spirits, primarily craft whiskey. Additionally, it relates to the creation of other non-alcoholic and low-alcoholic versions of other beverages such as wine (including grape or other fruit) or cider, and other craft distilled spirits such as brandy and vodka.

Method for creating a craft beer with low alcohol content

Novel catalytic materials and novel methods of preparing M-N&#x2014;C catalytic materials utilizing a sacrificial support approach and using inexpensive active polymers as the carbon and nitrogen source and readily available metal precursors are described.

Non-PGM catalyst for ORR based on pyrolysed poly-complexes

An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is provided on an integrated circuit. The integrated circuit includes a plurality of data inputs, a plurality of data outputs, a plurality of programming inputs and a plurality of logic units arranged as a matrix array. At least some of the logic units each comprise a Boolean logic computational unit having input terminals, output terminals, and programming terminals. The logic units are operated on a clocked basis such that each logic unit is controlled by the programming inputs. Each logic unit comprises a selector coupled to the input terminals and programmable to selectively couple input data from either the data inputs or output terminals of one or more other computational units to the computational unit. An array of programmable interconnects the data inputs of the matrix array and the output terminals of each of the logic units with input terminals of other logic units and to the data outputs of the matrix array. Each of the logic units and each of the selectors and the array of programmable interconnects are operated on a clocked basis such that Boolean functionality is determined during each clock cycle.

Reconfigurable array to compute digital algorithms

A configurable application specific product with a configurable input/output interface is described. The illustrative embodiment of the invention includes a single microcontroller and a microprocessor having a configurable I/O interface that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Configurable application specific standard product with configurable I/O

A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Configurable input/output interface for an application specific product

A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.

Programmable logic integrated circuit for digital algorithmic functions

A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Deterministic microcontroller with configurable input/output interface

A method and apparatus for a fully programmable and configurable application specific integrated circuit (FPCA). Programmable I/O cells are programmed for selected electrical characteristics, including power and ground. The circuit contains a functional core for programming the circuit, programmable I/O leads to connect to the programmable I/O cells, and programming logic and control for programming the functional core and I/O cells. Certain leads double as programmable I/O leads and programming control leads, and are used to communicate with the programming logic and control and the I/O cells. A method of programming the FPCA comprises the steps of asserting the programming control signal; applying programming voltage and ground to a respective two designated I/O cells' leads; isolating a plurality of the I/O cells from the programming signal; and programming an FPGA array in addition to the isolated I/O cells of the circuit.

Fully programmable and configurable application specific integrated circuit

A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display memory being partitioned into two frames of display memory with each frame having a plurality of subframes. The controller consisting of a read display memory decoder, a read display memory next subframe generator a read display memory latch and consisting of a write display memory decoder, a write display memory next subframe generator and write display memory latch.

Gerbil wheel memory

A symbol generator useful for stroke based and raster display systems provides the ability of generating ellipses and elliptical arc segments. A look-up table provides cosine and sine values for incremental angles which are multiplied by major and minor axis scale factors for a selected ellipse. Global input parameters permit rotation of all arcs and vectors to generate orthogonal projections, thereby producing 2-D and 3-D symbology.

Growing community of inventors

Albuquerque, NM, United States of America

Paul J Short