International Business Machines Corporation

Globalfoundries Inc.

Paul J Grzymkowski

John Robert Goss

Michael Richard Ouellette

Michael Anthony Ziegerhofer

Krishnendu Mondal

Aravindan J Busi

Kiran K Narayan

Robert J McMahon

Igor Arsovski

Jeanne P Bickford

Susan K Lichtensteiger

Thomas Gregory Sopchak

Troy Joseph Perry

David M Picozzi

Eric D Hunt-Schroeder

A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Pre-test power-optimized bin reassignment following selective voltage binning

Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

Application specific integrated circuit (ASIC) test screens and selection of such screens

A circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first listing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers. A method of controlling access to addressable circuit elements is also provided.

System and method for controlling access to addressable integrated circuits

A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable circuit elements. A selector distinguishes a first subset of unique identifiers from the first listing. A second storage element receives and stores the first subset in an arrangement that does not include an indication of the absence of any unique identifier of the first listing that is not included in the first subset. An output of second storage element allows a user of the integrated circuit to access one or more of the addressable circuit elements corresponding to the first subset of unique identifiers.

Structure for a system for controlling access to addressable integrated circuits

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Essex Junction, VT, United States of America

Paul J Grzymkowski