Intel Corporation

Paul J Diglio

Pooya Tadayon

David Shia

Joe F Walczyk

Eric J Moret

Joseph F Walczyk

Vineeth Abraham

Feras Eid

Xavier Francois Brun

Srikant Nekkanty

Wesley Brook Morgan

Karumbu Meyyappan

Christopher Wade Ackerman

Christopher Roy Schroeder

Craig Yost

Chandra Mohan Jha

John C Johnson

Pramod Malatkar

Dingying David Xu

Sergio Antonio Chan Arguedas

Kuang C Liu

Weihua Tang

Mohit Mamodia

Kyle Yazzie

Joseph B Petrini

Aastha Uppal

Nader N Abazarnia

Prabhakar Subrahmanyam

Arun Krishnamoorthy

Arnab Choudhury

Eric J M Moret

Jarett L Rinaldi

Ying-Feng Pang

Morten S Jensen

Phi Hung Thanh

David W Song

Rene J Sanchez

Todd Michael Young

Sruti Chigullapalli

Charles Clifton Fulton

Sufi Ahmed

Muhammad Ahmad

David Won-jun Song

Kelly Lofgreen

Lothar Kress

Robert Levi Bennett

Tewodros Wondimu

Jensen Stenberg

Varun Narayan

Sami Alelyani

Ruben Nunez Blanco

Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.

Directly impinging pressure modulated spray cooling and methods of target temperature control

The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. The method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. The method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. A corresponding system is also disclosed herein.

Method and device for fast, passive alignment in photonics assembly

An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.

Reworkable zero-force insertion electrical optical package socket and method

This disclosure describes systems, methods, and devices related to preventing water leakage from jet impingement applied to an integrated circuit under test. An integrated circuit testing apparatus for applying jet impingement to an integrated circuit may include an impingement chamber in contact with an integrated circuit being tested, the impingement chamber comprising water associated with cooling the integrated circuit; and an actuator-driven thermal management block including an air inlet configured to direct a flow of air into an immediate test environment for the integrated circuit to generate a positive pressure differential with respect to the water in the impingement chamber to prevent leakage of the water from the impingement chamber.

Enhanced jet impingement leak prevention for integrated circuit

A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

Integrated circuit die packages including a contiguous heat spreader

An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

Additively manufactured structures for heat dissipation from integrated circuit devices

Embodiments disclosed herein include a temperature control system. In an embodiment, the temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a plurality of fluid lines between the pump and the spray chamber, where individual ones of the plurality of fluid lines are configured to provide the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber.

Vacuum modulated two phase cooling loop efficiency and parallelism enhancement

Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

Thermally enhanced silicon back end layers for improved thermal performance

The present disclosure is directed to a system having a first loading component and a second loading component for applying load to a device during a test of the device, the first loading component is configured to be moveable with respect to the second loading component. The system includes a seal member arranged between the first loading component and the second loading component, the seal member is adapted to engage the device during testing so as to apply a load against the device during testing and provide sealing around a cavity positioned below the first loading component and above the device.

System and apparatus having a seal member for sealing of a device under test

Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.

Vacuum modulated two phase cooling loop performance enhancement

The present disclosure relates to a method including arranging multiple optical fibers between a die and a lid, wherein the die is bent and comprises multiple grooves, each optical fiber in or close to a separate groove; bonding the lid to the die to hold the multiple optical fibers in place in the multiple grooves, wherein the bonding comprises applying a bonding force non-uniformly across the lid to conform the lid to the bent die. A corresponding system is also disclosed herein.

Method and system for attaching optical fibers to warped photonic chips

Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.

Low-profile gimbal platform for high-resolution in situ co-planarity adjustment

Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

Double-beam test probe

An electrical-test apparatus is provided, which includes a plurality of tester interconnect structures cantilevered from a first side of a substrate. A base may be coupled to a second side of the substrate via one or more interconnect layers. The tester interconnect structures may contact corresponding interconnect structures of a device under test (DUT). In an example, the substrate is laterally movable relative to the DUT along a plane of the substrate, upon contact between the tester interconnect structures and the interconnect structures of the DUT.

Electrical testing apparatus with lateral movement of a probe support substrate

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Chandler, AZ, United States of America

Paul J Diglio