Synopsys, Inc.

Mentor Graphics Corporation

Berkeley Design Automation, Inc.

Paul Il Estrada

Jing Chyuarn Lin

Brent L Gregory

Amit Mehrotra

Emil F Girczyc

Srinivas Raghvendra

Trinanjan Chatterjee

Andrew Seawright

Chian-Min Richard Ho

Ping Fai Yeung

Tai An Ly

Kalyana C Mulam

Lawrence Curtis Widdoes, Jr

Jean-Charles Giomi

Paul Andrew Wilcox

Robert Kristianto Mardjuki

David Lansing Dill

Abhishek Somani

Kurt Johnson

Francois Le Grix

Simulation waveforms representative of simulation progress are generated and outputted for display. A netlist describing a circuit is accessed, and the circuit is simulated over a simulation runtime period. A simulation completion measurement is determined for the simulation runtime period, and a simulation waveform is generated based on the determined simulation completion measurement. Other simulation waveforms can be generated, for instance waveforms representative of a processing resource load over the simulation runtime period. Multiple simulation waveforms can be correlated and displayed in conjunction with each other, for instance in a common waveform interface.

Circuit simulation waveform generation and display

A system and process for utilizing probability distribution information about process parameters to quantify the probability of manufacturing process variation for variants of circuit designs in order to more efficiently analyze and simulate the designs.

Circuit instance variation probability system and method

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method for automatically searching for functional defects in a description of a circuit

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.

Architecture and methods for a hardware description language source

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

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Los Alto, CA, United States of America

Paul Il Estrada