Hewlett-packard Development Company, L.p.

Stmicroelectronics Gmbh

Stmicroelectronics Asia Pacific Pte Limited

Hewlett-packard Development, L.p.

Paul I Mikulan

Frank R Bryant

Simon Dodd

Reynaldo V Villavelez

Ning Ge

Kenneth J Stewart

Bee Ling Peh

Joseph M Torgerson

Lawrence H White

Chris Bakker

Gregory N Burton

Murray J Robinson

Teck-Khim Neo

Lonnie Byers

Bjorn Warloe

TeckKhim Neo

Rube M Ross

Virgina L Hwang

Michael Allen Godwin

A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.

Memory cell having closed curve structure

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other.

Circuit that selects EPROMs individually and in parallel

In an embodiment, to deter or delay counterfeiting/cloning of a replacement component of a host device, the replacement component is provided with a code value. The code value is generated from a value of at least one physical parameter of the replacement component and is stored on the replacement component. The host device determines whether the replacement component is authentic if the stored code value matches a reference code value.

Delaying or deterring counterfeiting and/or cloning of a component

A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.

A method of making inkjet print heads may include forming a first wafer including a sacrificial substrate layer, and a first dielectric layer thereon having first openings therein defining inkjet orifices. The method may also include forming a second wafer having inkjet chambers defined thereon, and joining the first and second wafers together so that each inkjet orifice is aligned with a respective inkjet chamber. The method may further include removing the sacrificial substrate layer thereby defining the inkjet print heads.

Methods of making inkjet print heads using a sacrificial substrate layer

Edges of a first conductive layer () and a silicate glass layer () extend adjacent one another along a via () extending to a semiconductor substrate (). An electrical conductor () extends through the via () into contact with the semiconductor substrate ().

Fluid ejection device comprising substrate contact via

A thermal inkjet printhead may include a substrate and a resistive layer. A thermal resistor may be formed in the resistive layer. A first metal layer may be between the substrate and a resistive layer having a thickness to form a power bus. A dielectric layer may be between the first metal layer and the resistive layer.

Power distribution in a thermal ink jet printhead

Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.

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Carrollton, TX, United States of America

Paul I Mikulan