Xilinx, Inc.

Advanced Micro Devices Corporation

Paul-Hugo Lamarche

Steven P Young

Brian C Gaide

Weiguang Lu

Eric E Edwards

Joe Eddie Leyba, Ii

Shadi M Barakat

Cheng Hsiang Hsieh

Bhuvanachandran K Nair

Arif Akram Siddiqi

Joe Eddie Ii Leyba

A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Method and apparatus for clock and data recovery

An embodiment of a method for control of signal level is disclosed. In such an embodiment, a number for a pre-cursor set, a number for a cursor set, and a number for a post-cursor set are set corresponding to a weighted contribution of a pre-cursor symbol, a weighted contribution of a cursor symbol, and a weighted contribution of a post-cursor symbol, respectively, for the signal level. A number associated with a high-impedance set is determined. The number associated with the high-impedance set is determined by subtracting the number for the pre-cursor set, the number for the cursor set, and the number for the post-cursor set from a total available amount of units. The high-impedance set provides no weighted contribution to the signal level. Data is transmitted using the signal level set responsive to the pre-cursor set, the cursor set, and the post-cursor set.

Signal level control

An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Configuration of a multi-die integrated circuit

A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

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San Jose, CA, United States of America

Paul-Hugo Lamarche