Adesto Technologies Corporation

Artemis Acquisition LLC

Paul Hill

Stephen Trinh

Bard Pedersen

Gideon Intrater

Danut Manea

Yongliang Wang

Richard V De Caro

Dian Wang

Richard V Caro

A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code. Controller circuits can generate the plurality of acknowledgement values, including first and second acknowledgement values in response to an operation indicated by the op code being completed, and first and third acknowledgement values in response to an operation indicated by the op code not being completed. Memory circuits can be configured to execute the operation indicated by the op code to access the nonvolatile memory cells, and indicate to the controller circuits whether or not the operation was completed. The first, second and third acknowledgement values can be different multi-bit values. Corresponding methods and systems are also disclosed.

Memory devices and methods having multiple acknowledgements in response to a same instruction

A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.

Memory devices and methods having instruction acknowledgement

A memory device can include: a non-volatile storage register configured to store an active reset polling enable bit that corresponds to a reset operation; a controller configured to control execution of the reset operation on the memory device; an operation completion indicator configured to provide a reset recovery indication external to the memory device when the reset operation has completed and the active reset polling enable bit is set; and a command decoder configured to receive a command to be executed on the memory device in response to the reset recovery indication.

Memory device alert of completion of internally self-timed power-up and reset operations

In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

Cached memory structure and operation

In one embodiment, a method of performing an active polling operation can include: (i) detecting a self-timed operation that is to be executed on a serial memory device; (ii) determining if an active polling mode has been enabled; (iii) determining when the self-timed operation has completed execution on the serial memory device; and (iv) providing a completion indication external to the serial memory device when the self-timed operation has completed execution and the active polling mode is enabled.

Serial memory device alert of an external host to completion of an internally self-timed operation

A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

Growing community of inventors

Eastleigh, United Kingdom

Paul Hill