Silicon Labs Cp, Inc.

Silicon Laboratories Inc.

Paul Highley

Kenneth Wilson Fernald

Donald E Alfano

Ka Yin Leung

Douglas S Piasecki

Douglas R Holberg

Danny Joe Allred

Brian Caloway

Alvin Chuck Storvik

Brent Wilson

Alvin C Storvik, Ii

Alan Storvik

Thomas Saroshan David

Randall Kent Sears

A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins

A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller. A memory interface allows the processing system to interface with the second portion of the memory, such that the processing system has an expanded memory capability.

Ethernet controller with excess on-board flash for microcontroller interface

An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.

Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation

An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.

Integrated circuit package including programmable oscillators

A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

Analog-to-digital converter with low power track-and-hold mode

A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. The method includes switching current in a switching operation from the input to the output through an inductive element and measuring the voltage/current parameters on the input and output. A control algorithm is then utilized to determine control parameters necessary to make a control move to effect the switching operation, the control algorithm utilizing as inputs the measured voltage/current parameters. A digital control system controls the switching operation, which digital control system is operable to be controlled by the control algorithm. Configuration data is received on a serial data bus for configuring the control algorithm. Thereafter, the operation of the control algorithm is modified in response to receiving the configuration information.

Digital control circuit for switching power supply with serial data input

Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Method and apparatus for calibration of a low frequency oscillator in a processor based system

A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins

Digital control circuit for switching power supply with pattern generator. A method is disclosed for converting DC power from a first voltage level on an input to a different voltage level on an output for delivery to a load. Current from the input is switched to the output through an inductive element with a plurality of switches, each of the switches driven by a waveform, all of the waveforms driving the switches referenced with a predetermined relationship to a master clock and all operating on a PWM duty cycle of the master clock. The voltage/current parameters on the input and output are measured and then a control algorithm is utilized to determine a change in the PWM duty cycle necessary to make a control move, the control algorithm utilizing as inputs the measured voltage/current parameters. A pre-stored waveform pattern for each of the waveforms is then modified to reflect the change in the PWM duty cycle required for the control move. After modification, the modified pattern is output to create the waveform and drive the respective switches.

Digital control circuit for switching power supply with pattern generator

Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein. The one of the addressable memory locations associated with both the generated address in the at least a portion of the address space in the processing system and the page pointer is then accessed

Paging scheme for a microcontroller for extending available register space

Method and apparatus for accessing paged memory with indirect addressing. A a method for changing pages of memory in an indirect addressed memory having a plurality of addressable locations therein is diclosed. An index indicative of the page of the memory being addressed is stored in a memory location. The memory is addressed with a direct address that selects one or more of the addressable locations in the addressed page of memory. An interrupt is received from a resource capable of generating an interrupt, which interrupt has associated therewith a defined one of the pages of memory. In response to generation of the interrupt, the value of the stored index t is changed o an index associated with the defined one of the pages of memory associated with the resource. In response to receiving a signal indicative of the generated interrupt having been serviced by a system that services interrupts, the stored index is changed to a different index.

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Austin, TX, United States of America

Paul Highley