Nxp B.v.

Nxp Usa, Inc.

Paul Hendrik Cappon

Marcin Grad

Taede Smedes

Michael A Stockinger

Gijs Jan De Raad

Dolphin Abessolo Bidzo

Chinmayee Kumari Panigrahi

Albert Jan Huitsing

Kiran B Gopal

Andrea Scarpa

Peter C De Jong

Sjoerd Bruinsma

A communications circuit includes transmitter circuitry for driving a differential signal on two die terminal. The transmitter circuitry includes two drive transistors who conductivity is controlled to provide a path from a common node to each of the die terminals. A string of one or more diodes is coupled to the common node to provide a path for discharging ESD current from the common node from an ESD event affecting either die terminal.

Differential transmitter circuitry with ESD circuitry

As disclosed herein, a level shift circuit includes devices that are responsive to an ESD signal for placing those devices in a specific condition in response to the ESD signal indicating an ESD event. In some embodiments, the devices are transistors in current paths that are placed in a condition such that during an ESD event, voltage differentials in the current paths across voltage domain boundaries do not damage the circuitry of the level shift circuit. In some embodiments, some of the same devices that are responsive to the ESD event are also responsive to a signal to that detects the absence of a power supply voltage of one of the domains and places those devices in a condition to disable the level shift circuit if the power supply voltage is not present.

Level shifter with ESD protection

An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

Snapback clamps for ESD protection with voltage limited, centralized triggering scheme

An integrated 'pull-down' driver circuit () is formed with a combination device consisting of an output driver transistor (N) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated 'pull-up' driver circuit may be formed with three corresponding PMOS transistors (P, P, P) connected as shown between a second power supply conductor and the conductive pad.

ESD-robust stacked driver

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Bias-insensitive trigger circuit for bigFET ESD supply protection

In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.

Growing community of inventors

Wijchen, Netherlands

Paul Hendrik Cappon