Intel Corporation

Paul H Wermer

David Gregory Figueroa

Kishore K Chakravorty

Debabrata Gupta

Brian A Kaiser

Paul A Koning

Steven N Towle

Ajit V Sathe

To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors

Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.

Circuit board with organic dielectric layer

To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive particles, and a thin, flexible apertured support that aligns the particles with corresponding lands on the IC package and substrate. A compression connector may also be used to electrically couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

Solderless electronics packaging and methods of manufacture

The present invention includes a dielectric. The dielectric includes a polymer that has a high dielectric constant. The polymer includes polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.

Polymeric dielectric material for high-energy density capacitors

Data processing system comprising ceramic/organic hybrid substrate with embedded capacitors

A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

Method of fabricating microelectronic package having a bumpless laminated interconnection layer

To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

Solderless electronics packaging

Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.

Capacitor

Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture

Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance

Microelectronic package having a bumpless laminated interconnection layer

The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.

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San Francisco, CA, United States of America

Paul H Wermer