Dmel Incorporated

Other

Paul H OuYang

Donald Liusie

The rate of discharge of the sense amplifier and bit lines in a memory circuit is controlled to simulate a boosted sense ground potential without requiring the use of a voltage regulator or precharged capacitors. The sense amplifier is electrically coupled to ground through a large transistor during a first period, which quickly discharges the sense amplifier toward ground potential to ensure a fast sense speed of the sense amplifier. During a subsequent period, the large transistor is turned off and the sense amplifier is electrically coupled to ground through a smaller transistor. The small transistor slowly discharges the sense amplifier towards ground, without reaching ground, until the active cycle is over and the discharge of the sense amplifier is terminated. By holding the sense amplifier above, but near, ground potential, the subthreshold leakage of non-selected memory cells is minimized so that the frequency of refresh may be decreased, thereby minimizing standby current.

Reduction of standby current

The precharge operation of a DRAM array in a non-multiplexed address interface is controlled so that the DRAM is precharged only if there is a change in the word line address. By precharging the DRAM only when a new word line is asserted, a significant power savings may be obtained. An activity monitor compares each new word line address with the previous word line address. If the activity monitor indicates that a new word line is asserted, a timing control circuit will precharge the DRAM, including equalizing the bit lines. If the activity monitor indicates that the word line is not changed, the timing control circuit does not precharge the DRAM. The timing control circuit includes a dummy precharge circuit and initiates a dummy precharge cycle in the beginning of each new cycle for timing purposes. The timing control circuit initiates the active cycle after the dummy precharge cycle regardless of whether a new word line is asserted or not.

Controlling the precharge operation in a DRAM array in a SRAM interface

An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and 'short-channel effects' are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation. The method of manufacturing such device is disclosed.

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San Jose, CA, United States of America

Paul H OuYang