Motorola Corporation

Motorola Solutions, Inc.

Symbol Technologies, LLC

Paul H Gailus

William J Turney

Lawrence F Cygan

Francis R Yester, Jr

Joseph A Charaska

Michael H Baker

Manuel P Gabato

Jeffrey B Wilhite

Mark A Gannon

John Janos Bozeki

Mark Rozental

Robert L Epsom

Kevin J McCallum

Joshua E Dorevitch

Robert E Stengel

Ovadia Grossman

Moshe Ben-Ayun

Anthony P Van Den Heuvel

William J Martin

Terry K Mansfield

Edward T Clark

Rostyslaw Zbotaniw

Lawrence Marvin Ecklund

Steven F Gillig

David H Minasi

Armando J Gonzalez

Ronald H Chapman

Edward Vincent Louis

Stephen B Einbinder

Chong Hin Chee

Shafiullah Syed

Anthony John Wray

Vadim Dubov

Jeffrey B White

Babak Bastani

A method and apparatus for compensation of noise in a Radio Frequency Identification (RFID) device through modulation of a received signal is described. The method includes determining an amplitude signal proportional to an amplitude of a transmitter signal and associated noise; processing the amplitude signal to derive a correction signal; and modulating a received signal during a receive period with the correction signal to substantially remove the associated noise from the received signal. An RFID device and an RFID transceiver integrated circuit (IC) are also described.

Apparatus and method for compensation of AM noise in RFID devices through modulation of a received signal

A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Method and apparatus for single port modulation using a fractional-N modulator

A post-mixer amplifier device which receives and processes signals for use in a software-defined radio integrated circuit is provided. The post-mixer amplifier device includes but is not limited to a voltage amplifier having first and second inputs and a first output, a positive signal output connected with the first output of the voltage amplifier, and a positive signal input connected with a first bipolar junction transistor along a first pathway. The first bipolar junction transistor includes but is not limited to a first collector connected with a the first input of the voltage amplifier and a first emitter connected with an second output of the push-pull unity gain follower and forming a first current feedback pathway. The first bipolar junction transistor is driven with a passive resistive load.

Flexible low noise, high linearity, high frequency, low power, fully differential mixer and class AB post-mixer amplifier system for SDR applications

A wireless communication unit includes a linearised transmitter having a forward path and a feedback path, respectively comprising at least one up-mixer and down-mixer, and forming two loops in quadrature. A phase training signal is applied to the at least one down-mixer in the feedback path in an open loop mode of operation to identify a loop phase adjustment to be applied. At least one of the two loops is switched to a closed loop mode of operation and the loop phase adjustment is applied to at least one up-mixer located in the forward path.

Wireless communication unit, linearised transmitter circuit and method of linearising therein

A wireless communication unit includes a frequency generation circuit, and a linearised transmitter operably coupled to the frequency generation circuit and having a forward path for routing a signal to be transmitted; and a feedback path, operably coupled to a power amplifier and the forward path for feeding back a portion of the signal to be transmitted. The feedback path and forward path form two loops in quadrature. The frequency generation circuit includes independent phase shift elements arranged to independently phase shift the two loops in quadrature ('I' and 'Q').

A feedback loop with an adjustable closed loop frequency response. The feedback loop contains adjustable pole () and adjustable zero elements () for changing the pole and/or zero locations in the feedback loop's loop frequency response thereby changing the closed loop frequency response of the feedback loop. In one embodiment, the feedback loop is a Cartesian feedback loop suitable for use in a radio transmitter.

Feedback loop with adjustable bandwidth

A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.

Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter

A frequency synthesizer includes: a frequency source generating a reference signal that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit, a loop filter, a controlled oscillator that generates an output signal at an output, and a loop divide circuit; a non-linear circuit element at an input of the phase detector circuit, which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller controlling the loop divide circuit and the non-linear circuit element. The frequency synthesizer further includes a dither circuit that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller to the non-linear circuit element, thereby, providing a jittered reference signal to the non-linear circuit element for attenuating the at least one spurious signal at the output.

Method and apparatus for spur reduction in a frequency synthesizer

A method and apparatus for reducing in-band spurs in a fractional-N synthesizer () includes generating a compensated current signal by a charge pump () coupled to a phase detector (). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (). The dithered compensated current signal is then passed through the loop filter () for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.

Method and apparatus for reducing spurs in a fractional-N synthesizer

A system and method for performing baseband phase shifting in a Cartesian feedback system includes a forward path for receiving an input baseband signal having two components, and performing up-conversion to output a RF signal; a power amplifier for amplifying the RF signal output from the forward path; and a feedback path for down-converting at least a sample of the output from the power amplifier to a feedback baseband signal comprising two components, and providing the feedback baseband signal to the forward path in order to be summed with the input baseband signal at a summing junction and before the loop filter. The forward path includes a baseband phase shifter for adjusting the baseband signal output from the summing junction in order to compensate for any phase shifts induced in the system.

System and method for performing baseband phase shifting in a Cartesian feedback system

A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches

A DPC () that includes: a frequency source (); a delay-locked loop () for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device () having a DPS () and a DAC () for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit () for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell () having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal () having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Method and apparatus for frequency synthesis

A delay-locked loopthat includes: an adjustable frequency source () for generating a clock signal () having an adjustable frequency; an adjustment and tap selection controller () for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line () configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit () for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Adjustable frequency delay-locked loop

A power amplifier that includes: an input drive controller () for receiving an input signal () and for generating from the input signal at least a first drive signal (), a second drive signal (), and a third drive signal (); an outphasing amplifier network () coupled to the input drive controller that includes at least a first outphasing amplifier () for amplifying the first drive signal and a second outphasing amplifier () for amplifying the second drive signal; a peaking amplifier network () coupled to the input drive controller that includes at least a first peaking amplifier () for amplifying the third drive signal; and a combining network () coupled to the outphasing amplifier network and the peaking amplifier network for combining at least the amplified first, second and third drive signals to generate an output signal at a load.

Method and apparatus for an enhanced efficiency power amplifier

An isolator eliminator for a linear transmitter receives a plurality of digital samples of an information signal and a drive signal sampled from a feedback loop at periodic time intervals and, responsive to processing the digital samples, provides high accuracy phase and level correction signals to the feedback loop. The phase and level correction signals maintain stable, linear operation of the feedback loop and limit splatter. In a preferred embodiment, the isolator eliminator includes a digital signal processor such that multiple communication protocols may be accommodated by changing software code executed by the processor.

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Prospect Heights, IL, United States of America

Paul H Gailus