Texas Instruments Corporation

Nvidia Corporation

Paul H Fontaine

Abdellatif Bellaouar

Anand Ganesh Dabak

Anuj Batra

Jaiganesh Balakrishnan

Ranjit Gharpurey

Bertan Bakkaloglu

Heng-Chih Lin

Pascal Audinot

Michel Frechette

Ahmed N Mohieldin

Mikael Guenais

A sigma-delta analog-to-digital converter includes an input transconductance stage that provides an analog input current proportional to an analog input voltage and a current summing stage that generates an analog error signal corresponding to a difference between the analog input current and a feedback current. The sigma-delta analog-to-digital converter also includes a forward signal path that processes the analog error signal to provide a digital output signal corresponding to the analog input voltage. Additionally, the sigma-delta analog-to-digital converter includes a feedback path that includes a current steering digital-to-analog converter having both sourcing and sinking current sources, wherein currents provided by the sourcing and sinking current sources are steerable and connected to directly provide the feedback current based on the digital output signal. A sigma-delta analog-to-digital converter operating method is also provided.

Sigma-delta analog to digital converter with improved feedback

A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of 11/32, 1/2, 5/8 and 3/4.

Time-frequency interleaved orthogonal frequency division multiplexing ultra wide band physical layer

System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Ultra-wideband communications system devices

A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.

Low-noise sigma-delta frequency synthesizer

A receiveris provided. The receivercomprises an in-phase analog-to-digital converteroperable to detect a saturation condition of the in-phase analog-to-digital converterand to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converterto remove the in-phase analog-to-digital converterfrom the saturation condition and a in-phase digital filteroperable to adjust a gain applied to a digital input to the in-phase digital filterfrom the in-phase analog-to-digital converter, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter. In an embodiment, the receiveralso comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converterand the in-phase digital filtercomprise an intermediate frequency receiver.

Digital detection of blockers for wireless receiver

The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (). The system provides a primary DAC function () and a supplemental DAC function (), as well as a control function (). The control function is utilized to determine a first bit step () of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step () of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (), to provide a programming control word for the programmable semiconductor component.

Versatile system for high resolution device calibration

A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, K , of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.

Efficient modulation compensation of sigma delta fractional phase locked loop

A wireless telephone ( ) is disclosed, in which audio input/output circuitry ( ) includes a digital-to-analog conversion function ( ) for producing an analog output signal (s(t)) based upon a digital baseband signal (S) from a digital signal processor ( ). The digital-to-analog conversion function ( ) includes first and second &Sgr;&Dgr; modulators ( ), each of which are controlled by a sampling clock generated by a dual frequency divider ( ) controlled by the first &Sgr;&Dgr; modulator ( ). A sampling latch ( ) samples the digital baseband signal synchronously with the sampling clock. The second &Sgr;&Dgr; modulator ( ) selects an oversampling multiple that is applied to a digit filter ( ) along with the sampled signal from the sampling latch ( ). The digital filter ( ) reconstructs a digital signal from the sampled value and the oversampling multiple that is the equivalent of that reconstructed by the decimation of an over sampled signal. The reconstructed signal is converted to analog by a digital-to-analog converter ( ). However, the digital filter ( ) and DAC ( ) can operate at a much lower frequency than in conventional circuits, thus providing excellent noise performance without requiring high frequency clocking.

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Plano, TX, United States of America

Paul H Fontaine