International Business Machines Corporation

Paul H Bergeron

Jason D Hibbeler

Gustavo Enrique Tellez

David James Hathaway

David E Lackey

Alvar Antonio Dean

Larry Wissel

Roger Paul Gregor

Keith M Carrig

Keith W Lallier

Harold E Reindel

Jerome B Hickson, Jr

Roger K Jackson

Kurt D Carpenter

Elba K Malone

Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

Systematic yield in semiconductor manufacture

Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on a layer above the lower layer are formed on a more planar surface and thus are more likely to function properly. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.

A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Latch clustering for power optimization

A wire packing method for packing wire segments in wiring bays of large-scale integrated circuit devices and integrated circuit devices produced employing such a method. Each wiring segment to be placed in a channel of a wiring bay is assigned a score in accordance with criteria developed for the particular application. The start point, end point and a segment identifier is recorded for each segment to be packed. For each channel, segments which can be considered candidates for packing in that channel are extracted from the list. For that channel, moving forwardly from one end of the channel, at the end point of each segment, a total score is calculated by adding to the score of that segment a best score occurring before the start point of the segment. If the total score exceeds a present value of a best string score for nonoverlapping segments, the present value of the best string score is replaced by the new total score, otherwise the present value of the best string score is retained. When the other end of the bay is reached, moving back towards the first end, segments are assigned to the channel for which the total score therefor exceeded the then-present value of the best string score and which do not overlap already-assigned segments.

Bay packing method and integrated circuit employing same

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South Burlington, VT, United States of America

Paul H Bergeron