Nvidia Corporation

Google Inc.

Paul Gyugyi

Sameer Nanda

Thomas A Maufer

Paul J Sidenblad

Radoslav Danilak

Anand Rajagopalan

Ashutosh Jha

Dmitry Vyshetsky

Howard Tsai

Roman Surgutchik

Victor Lin

Andrei Pascovici

Shlomi Regev

Jianghai Zhu

Brad W Simeral

Nirmal Raj Saxena

Edward L Riegelsberger

Robert William Chapman

Neal Meininger

Tony C Tam

Dmitry Vyshetski

Raymond A Lui

Implementations set forth herein relate to management of casting requests and user inputs at a rechargeable device, which provides access to an automated assistant and is capable of rendering data that is cast from a separate device. Casting requests can be handled by the rechargeable device despite a device SoC of the rechargeable device operating in a sleep mode. Furthermore, spoken utterances provided by a user for invoking the automated assistant can also be adaptively managed by the rechargeable device in order mitigate idle power consumption by the device SoC. Such spoken utterances can be initially processed by a digital signal processor (DSP), and, based on one or more features (e.g., voice characteristic, conformity to a particular invocation phrase, etc.) of the spoken utterance, the device SoC can be initialized for an amount of time that is selected based on the features of the spoken utterance.

Adaptive management of casting requests and/or user inputs at a rechargeable device

Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.

Virtualization of chip enables

A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.

Method and system for improved flash controller commands selection

Described are data structures, and methodology for forming same, for network protocol processing. A method for creating data structures for firewalling and network address translating is described. A method for creating data structures for physical layer addressing is described. A method for security protocol support using a data structure is described. A method for creating at least one data structure sized responsive to whether a firewall is activated is described. A data structure for routing packets is described. A method of forming hashing table chains is described. Additionally, method and apparatus for tracking packet states is described. More particularly, Transmission Control Protocol ('TCP') tracking of states for packets is described. In an embodiment, a division between software states and hardware states is made as a packet is processed by both software and hardware. Additionally, method and apparatus for network protocol processing are described. For example, a packet for network address translation having a media access control header is obtained, from which information, including the media access control header, is obtained. The information is parsed into one or more data structures. It is determined whether a network processing unit is in a first round processing mode, or a second round pass-through mode.

Data structures and state tracking for network protocol processing

A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.

Method and system for improving direct memory access offload

Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

Method and system for data structure management

An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.

Method and system for fast two bit error correction

A system and methods of uploading payload data to user buffers in system memory and of uploading partially processed frame data to legacy buffers allocated in Operating System memory space are described. User buffers are stored in a portion of system memory allocated to an application program, therefore data stored in user buffers does not need to be copied from another portion of system memory to the portion of system memory allocated to the application program. When partially processed frame data is uploaded by hardware to a legacy buffer in system memory, a tag, uniquely identifying the legacy buffer location is transferred by the hardware to a TCP stack, enabling the TCP stack to locate the legacy buffer.

Uploading TCP frame data to user buffers and buffers in system memory

A method and apparatus for transmitting commands between a TCP stack and an offload unit and for communicating receive and transmit data buffer locations is described. A command ring buffer stored in system memory is used to transmit commands from the TCP stack to the offload unit and to transmit command status from the offload unit to the TCP stack. A notification ring buffer is used to transmit connection information from the offload unit to the TCP stack. Other ring buffers are used to transmit locations of transmit buffers or receive buffers stored in system memory from the TCP stack to the offload unit.

Transmitting commands and information between a TCP/IP stack and an offload unit

Method and apparatus for packet processing by re-insertion into network interface circuitry. A method for handling a burst of packets sent to network interface circuitry includes checking for a connection table entry for received packets, and responsive to non-existence of the connection table entry for the received packets, sending the packets to network interface software for processing. The network interface software processing includes: building the connection table entry; processing the packets; and sending the packets as processed to the network interface circuitry. Additionally, a method for re-inserting a packet responsive to an active audit mode is described.

Packet processing with re-insertion into network interface circuitry

A computing system offloads packet classification from a central processing unit to a graphics processing unit. In one implementation input data packets to be classified are represented as a first texture, classification rules are represented as a second texture, and a shading operation is performed to classify packets.

Apparatus, system, and method for offloading packet classification

Method and apparatus for network protocol filtering of a packet is described. An index to a table is obtained and stored to travel with the packet. The index is obtainable to access the table to obtain packet information. In particular, a method for inbound network address translation packet filtering and a method for outbound packet filtering are described.

Network protocol processing for filtering packets

An embodiment of the invention includes a first pseudo-random number generator that is configured to produce a first sequence of values at a first clock rate. Also, a second pseudo-random number generator is configured to produce a second sequence of values at a second clock rate. The second clock rate is based on the first sequence of values and the first clock rate. A logical module is connected to the first pseudo-random number generator and the second pseudo-random number generator. The logical module is configured to produce an output value based on at least a portion of a value from the first sequence of values and at least a portion of a value from the second sequence of values.

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Sunnyvale, CA, United States of America

Paul Gyugyi