The University of Texas System

Hewlett Packard Enterprise Development LP

Texas A&M University System

Paul Gratz

Stephen William Keckler

Boris Grot

Douglas Christopher Burger

Robert Greg McDonald

Ayman Abouelwafa

Karthikevan Sankaralingam

Ramadass Nagarajan

Changkyu Kim

Haiming Liu

Lakshminarasimhan Sethumadhavan

Nitya Ranganathan

Steven William Keckler

Narasimha Reddy Annapareddy

Chih-Chieh Chou

Chandrahas Tirumulasetty

Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.

Methods, systems, and computer readable media for performing page fault handling

The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another.

Method and apparatus for congestion-aware routing in a computer interconnection network

A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.

Dynamically composing processor cores to form logical processors

Growing community of inventors

Austin, TX, United States of America

Paul Gratz