Infineon Technologies Ag

Qimonda Ag

Paul Georg Lindt

Peter Gregorius

Heinz Mattes

Karthik S Gopalakrishnan

Hamid Partovi

Luca Ravezzi

Andreas Blum

Michael Brünnert

A method of synchronization of a digital circuit includes selecting a first site and a second site from a plurality of different sites of the digital circuit where a signal to be synchronized occurs; passing a first signal, which is the signal to be synchronized of the first site, via a first line that starts at the first site, ends at the second site, and contacts each of the sites just once, to the second site; passing a second signal, which is the signal to be synchronized of the second site, via a second line that starts at the second site, ends at the first site, and contacts each of the sites just once, to the first site; determining, for each site, a first phase shift between the signal to be synchronized of this site and the first signal, and a second phase shift between the signal to be synchronized of this site and the second signal; and determining, from the first and second phase shifts of each site, a delay for each site, with which the signal to be synchronized of the respective site is delayed for the synchronization.

Synchronization of a digital circuit

A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

Clock data recovery circuit with circuit loop disablement

To estimate physical properties of a wired or wireless transmission channel it is proposed to sample a signal, received via the transmission channel, for example a system response of the corresponding transmission system, in order, on the basis of the sampled values thus obtained, to ascertain the moments of the order 0 . . . n of the received signal. Using these moments of the order 0 . . . n, n parameters of a transmission function of the transmission channel can be determined, wherein the parameters can be polynomial coefficients, zero points or coefficients of a residual notation of the transmission function. Using this transmission function the physical properties of the transmission channel, such as the attenuation and dispersion properties, can be determined exactly or at least approximately assessed.

Method and device for estimating channel properties of a transmission channel

A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

Method and filter arrangement for digital recursive filtering in the time domain

Method for measuring and compensating skews of data transmission lines connecting at least one data transmission device with a data reception device via a parallel data bus comprising for each data transmission line the following steps: measuring the relative time delay of the data transmission line by transmitting a determined sequence of measurement vectors (MV) each consisting of an alternating bit pattern via said data transmission line, wherein the bit alternation frequency is halfed with every transmitted measurement vector (MV); comparing the received measurement vectors (MV') transmitted via said data transmission line with corresponding reference vectors (RV) stored in said data reception device; shifting the received measurement vectors by inserting data unit intervals (UI) until a received measurement vector (MV&#x2032;) matches a corresponding reference vector (RV); calculating a relative skew of the data transmission line depending of the number of inserted data unit intervals (UI) with respect to a slowest data transmission line; and compensating the calculated relative skew of the data transmission line by means of delay elements switched in response to the calculated relative skew.

Method for measuring and compensating for skews of data transmission lines by compensating for skew by delay elements switched in response to the calculated reative skew

Circuit board having a plurality of bus lines (), which run on the circuit board () essentially parallel to a preferred direction of the circuit board (), and having at least one integrated circuit () for the high-speed data processing of data, which integrated circuit is arranged on the circuit board (), is integrated in a housing () having a plurality of housing sides () and has a plurality of parallel interfaces for connection to the bus lines (), in which case the housing sides () of the integrated circuits () are oriented at an inclination with respect to the preferred direction of the circuit board ().

Circuit board having an integrated circuit for high-speed data processing

A memory buffer for a memory module board which is connected via a signal line (-) to a plurality of memory modules (-) mounted on said memory module board having different signal line lengths, wherein the memory buffer () comprises for each signal line (-) a corresponding integration circuit (-) for integrating the transmission time of a measurement pulse transmitted via said signal line (-) between said memory buffer () and a memory module (-) connected to said signal line (-).

Method for measuring the delay time of a signal line

A coupling configuration for connecting an optical conductor to an opto-receiver has a parabolic mirror or a spherical mirror that reflects light emerging from the optical conductor onto a launching mirror through which the light is launched into the opto-receiver. Such a configuration is largely adjustment-free and therefore particularly suitable for the connection of single-mode fibers (SMF).

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Donauwörth, Germany

Paul Georg Lindt