Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

Paul Geoffrey Lowney

Michael C Adler

Robert S Cohn

Steven O Hobbs

David William Goodwin

Richard Eugene Kessler

James B Keller

Norman Rubin

Stephen C Root

David P Hunter

David W Goodwin

Sharon Lea Smith

Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Computer method and apparatus for safe instrumentation of reverse executable program modules

A method for permitting software optimization tools, software instrumenting tools and other analysis tools to re-write executables having mixed instructions and data uses a data structure having an entry for each multi-bit word in an executable file. Each entry of the data structure includes a number of flags that are set to identify the type of the multi-bit word in the associated line of the executable file. The types include instruction, data and unclassified. Each entry also includes a flag that indicates that the multi-bit word should not be optimized and a flag indicating that the multi-bit word is a problem branch. The no-optimize and problem branch flags may be used to identify multi-bit words that may be either branch instructions or data, and to ensure that such multi-bit words are not affected by optimization or other rewriting of the executable. In addition, a problem fall through flag is provided to maintain program flow for possible fall through code segments.

Mechanism for re-writing an executable having mixed code and data

A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

Method and apparatus for balancing load vs. store access to a primary

A profile feedback optimization system is provided. The system accepts as input an original application and produces an optimized version of the application. The system first instruments the original application through an instrumentation process such that when it executes, it generates profile data. During instrumentation, the system configures images in the application to trap any function calls to critical functions. This allows the instrumented version of the application to execute transparently and appear as the original version. The instrumentation process converts each original image of the application to a version that references other instrumented images. The instrumentation process also configures the operating system to execute the instrumented version instead of the original version when the user selects the application for execution. Once instrumented, the instrumented application is executed. During execution, profile data produced from the instrumented images is saved in a database. Once profile data has been generated, an optimization process is used to optimize the original version of the application based upon the profile data. The optimized version is also configured to execute just as the original application, but references optimized images instead of original images.

User transparent mechanism for profile feedback optimization

Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.

Software mechanism for accurately handling exceptions generated by

A method of compiling an application to reduce the occurrence of speculative exceptions is described. The method includes the steps of compiling the application to provide a speculation table and an executable file, and obtaining profile information about said compiled application using representative data sets. The compiler includes a scheduler unit for rearranging the order of the instructions in the application to provide optimal performance. The speculation table comprises a number of entries corresponding to the instructions of the application, each entry including a tag identifying the instruction and a semaphore indicating whether or not the instruction is likely to cause an exception. The executable file is run using a number of representative data sets to profile information identifying those instructions that result in exceptions, and the tag of the instruction is stored in a log file. After the profiling has completed, the tags of the instructions causing exceptions are used to set the semaphores in the speculation table corresponding to the tag. The application is then re-compiled. During the recompilation, those instructions with their semaphores set; i.e. those instructions causing exceptions, will not be speculatively scheduled by the compiler.

Software mechanism for reducing exceptions generated by speculatively

Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine in the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of a eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handing routine if the semaphore indicates that an exception occurred when the speculative instruction was executed, and the predicate is true, which indicates that the speculative instruction was properly executed.

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Concord, MA, United States of America

Paul Geoffrey Lowney