Cavium, Inc.

Paul G Scrobohaci

Bryan Chin

Ahmed Shahid

Daniel A Katz

Shahe Hagop Krakirian

Wu Ye

Leo Chen

Wilson Parkhurst Snyder, Ii

Najeeb Imran Ansari

Albert Ma

Anna Kujtkowski

Scott A Lurndal

Jeffrey Schroeder

Chee Hu

Michael Carns

Jeff Pangborn

Yoganand Chillarige

Brian Hunter

In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.

Multiple ethernet ports and port types using a shared data path

Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.

Distributed interrupt scheme in a multi-processor system

In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Approach for interfacing a pipeline with two or more interfaces in a processor

In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.

Processor with dedicated virtual functions and dynamic assignment of functional resources

In one embodiment, a system includes a station circuit. The station circuit includes a data layer and a transport layer. The station circuit is capable of a source mode and a destination mode. The data layer of the station circuit in source mode disassembles a source packet into one or more source parcels and sends the one or more source parcels to the transport layer. The station circuit in destination mode receives the one or more destination parcels over a ring at its transport layer, reassembles the one or more destination parcels into a destination packet, and delivers the destination packet from the transport layer to the data layer. The transport layer of the station circuit in source mode transmits the one or more source parcels over the ring. The transport layer of the station circuit in destination mode receives the one or more destination parcels over the ring.

High speed variable bandwidth ring-based system

Growing community of inventors

Menlo Park, CA, United States of America

Paul G Scrobohaci