Advanced Micro Devices Corporation

Dsp Group Limited

Legerity, Inc.

Dps Group, Inc.

Advinced Micro Devices, Inc.

Paul G Schnizlein

Alan R Hendrickson

Stephen T Janesch

David E Norris

Peter E Sheldon

Dale E Gulick

Larry David Hewitt

Alfredo R Linz

David N Suggs

Carlin D Cabler

Glen W Brown

Geoffrey E Brehmer

Michael E Spak

Jeffrey M Blumenthal

Ryan E Feemster

Jacqueline E Mullins

Martin P Soques

Michael Hogan

David J Guercio

Alan T Torok

Alan F Hendrickson

Javier V Magana

Donald M Walters, Jr

Kenneth Tallo

James J Covell

Ed Bell

Geoffrey E Brehner

Wen-Tsung F Tang

A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data. The method includes steps of (a) performing a carrier recovery during the preamble of a received frame, (b) storing a digital word indicative of a recovered carrier frequency at the end of the preamble, (c) continuing the carrier recovery during the payload portion of the received frame, (d) using the stored digital word to set an initial frequency for carrier recovery at the start of a subsequent frame, and (e) repeating said steps (a)-(d) for each frame in the series of data frames.

Compensation of frequency pulling in a time-division duplexing transceiver

The invention is, in its various aspects, an apparatus and a method for scanning a keypad or a keyboard. The apparatus comprises a keypad and an integrated circuit. The keypad includes a plurality of chained resistors and a plurality of key switches. Each of the plurality of key switches is tied to a common node at a first terminal thereof and tapping the chained resistors at a second node thereof. Each of the key switches generates a signal indicative of the respective key switch being pressed when the key switch is pressed. The integrated circuit is capable of receiving the generated signal. The integrated circuit furthermore includes an analog to digital converter capable of generating a reference signal and a circuit capable of determining which key switch has been pressed from the magnitude of the generated voltage signal and the reference signal. The method for scanning a keypad comprises generating a voltage signal whose magnitude indicates which key is being pressed, and determining from the magnitude of the generated voltage signal which key was pressed.

Keypad scanning with few pins

A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Integrated circuit reset incorporating battery monitor and watchdog timer

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

Described herein is a system and method of disabling D bits in a CT2 MUX signaling channel. When the bit count equals the bit location of where the D bits are typically located in the signaling channel of a CT2 MUX, circuitry of the present invention disables a D bit enable signal from being processed. The D bit enable signal would typically allow a transmitter and receiver to, respectively, send a bit as a D bit, or process a received bit as a D bit. The suffix of the CT2 MUX, consisting of D bits, is unaffected by the present invention.

Training preamble added to CT2 muxes in a CT2 wireless telecommunications system

A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals. The system control functions circuit comprises a microcontroller, connected to the codec, for controlling the baseband chip, a memory accessible by the microcontroller for storing control instructions, an interrupt controller connected to the microcontroller, a parallel port connected to the interrupt controller, a wake-up timer connected to the interrupt controller, a clock generator connected to the microcontroller, and a synchronous serial port connected to the interrupt controller.

Narrowband digital cordless telephone

A battery monitor with programmable voltage references. The battery monitor includes a comparator circuit connected to a battery for receiving a voltage level thereof and to a voltage reference circuit for receiving a at least one reference voltage generated thereby. A trim circuit is connected to the voltage reference circuit for adjusting the reference voltage(s) and generated by the voltage reference circuit. The comparator circuit compares the voltage level of the battery with the reference voltage(s) generates an output based on the relative value of the battery voltage compared to the reference voltage(s). The trim circuit is programmable and includes a microprocessor connected to a programmable register and a memory. The microprocessor obtains trim data from the memory and writes the trim data to the programmable register.

Battery monitor with software trim

A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Phase detector for carrier recovery in a DQPSK receiver

A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.

FIFO and system synchronization system and method

A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initializing value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

Carrier-recovery loop with stored initialization in a radio receiver

A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier reference signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data. The digital differential decoder produces a digital complex-signal output that can be quantized in a digital slicer to decode the plurality of binary bits transmitted through the data symbols. All these operations are performed on digital signals with basic digital circuit elements, thus resulting in a repeatable robust receiver design without complex hardware components.

Passband DQPSK detector for a digital communications receiver

A system and method of muting a voice signal in a wireless communication system when an 'all zeros' condition of a digitized serial voice input signal is detected. The mute signal which is generated when a zeros condition occurs is provided to a voice processor to initiate a mute algorithm to mute the processing of incoming voice data during the sample time of the zeros condition.

System and method for implementing a mute voice signal upon reception of

A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardware. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention. These gain coefficients are chosen to be powers of two, simplifying the process of multiplying them with the digital error signal. The gain coefficients are read from a memory, making the loop filter easily programmable. By changing the gain coefficients during operation of the receiver, the carrier-recovery loop can be placed in one of the several operating modes, including acquisition, tracking, and hold. The receiver can be configured with the appropriate values of the gain coefficients for each operating mode during the initial assembly and during subsequent reconfigurations.

Programmable loop filter for carrier recovery in a radio receiver

A system and method is described herein for providing FDD and TDD modes of operation for a wireless communications device. The system includes a clock signal for FDD mode operation, a separate clock signal for TDD mode operation, where the TDD mode clock is twice the frequency of the FDD clock. Additionally, a counter is provided for counting bit times during a transmission or receive frame. The clock counter is reloaded after a pre-specified count is achieved. The pre-specified count is twice as great in TDD mode operation than in FDD mode operation to account for the fact that the bit periods are twice as long in FDD operation than during TDD operation since transmit and receive are at different frequencies and are not sharing the same channel.

System and method for providing FDD and TDD modes of operation for a

A telephone for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The telephone comprises a radio interface connection with the frame formatter, a FIFO/codec interface conductively coupled to the frame formatter, an interrupt interface conductively coupled to the frame formatter, a data control logic interface conductively coupled to the frame formatter, and a microcontroller interface conductively coupled to the frame formatter.

Growing community of inventors

Austin, TX, United States of America

Paul G Schnizlein