International Business Machines Corporation

Paul G Ferro

Robert Dov Herzl

Robert J Devins

Kenneth A Mahler

David W Milton

Mark E Kautzman

The time, effort and expense required to develop verification software for testing and de-bugging system-on-chip (SOC) designs represents a considerable investment. According to the method of the present invention, a portion of such verification software may be re-used in an operating system (OS) (i.e., a system used for, e.g., general business, technical or scientific applications as opposed to software testing) to capitalize on the investment. The verification software includes low-level device drivers (LLDDs) which were coded for and paired with specific device designs ('cores') throughout the verification process, and were consequently also verified (i.e., de-bugged) in the process. Thus, the low-level device drivers represent reliable software with detailed knowledge of the corresponding devices. By developing a thin middle-level device driver layer of software to interface between a particular OS and the lower-level device drivers, the LLDDs can be re-used in an OS that uses devices that the LLDDs were designed for. This frees SOC customers from having to develop low-level software and instead allows them to concentrate on developing their particular applications, or 'value-added' software.

Method for re-using system-on-chip verification software in an operating system

Processor-independent system-on-chip verification for embedded processor systems

A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (&ldquo;cores&rdquo;) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.

Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs

Growing community of inventors

South Burlington, VT, United States of America

Paul G Ferro