Infineon Technologies Ag

Paul Fugger

Alberto Canella

Filip Netrval

The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units () which process a program (). A control unit () is provided for independent control of the individual arithmetic units (), which control unit () reads and evaluates the flags () which are specific to the arithmetic units, and deactivates those arithmetic units () whose associated flag is not set, so that a subroutine is carried out only by those arithmetic units () whose flags are set.

SIMD processor with a subroutine control unit

An addition circuit for digital data includes a digital adder for the addition of digital input data values present at data inputs of the digital adder to form a summation output data value, at an output of the digital adder. The data inputs have a predetermined data bit width n. A saturation circuit for limits the summation output data value present at a data input of the saturation circuit to be within a range determined by an upper threshold data value and a lower threshold data value. The n&#x2212;m least significant data bits of the summation output data value are present directly at the data input of the saturation circuit, whereas the m most significant data bits of the summation output data value are switched through to the data input of the saturation circuit via a clock-state-controlled latch register.

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Graz, Austria

Paul Fugger