Synopsys, Inc.

Paul Frain

Qing Zhang

Adrian Wrixon

Maurice Keller

Srivathsan Krishna Mohan

Anton Belov

A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. The timing signal has a plurality of attributes varying with the propagation including a depth value and/or a distance value. The method comprises determining a derating factor for a delay of at least one of the plurality of timing arcs depending on the depth and/or the distance value of the timing signal at a pin of said at least one timing arc, and generating a timing report based on the derating factor.

Pessimism reduction in static timing analysis

A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a corresponding vector set. Each vector set is derived from the original vector set. A final set of memory nodes for the sequential circuit cell can be calculated by subtracting one node set from another node set. In one embodiment, the method can further include pruning non-gate connected nodes from the final node set.

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Dublin, Ireland

Paul Frain